| Week | Day | Date | Topic | Reading | Lab | Release | Deadline | Comments |
|---|---|---|---|---|---|---|---|---|
| 1 | Tue | 22 Jan | Administrivia
[]
Introduction [] |
Sections 1.1 and 1.2 | Lab 0: Intro to VM/Git | |||
| Thu | 24 Jan | Logic & Gates [] | Appendix A.1, A.2, and A.3 Quiz | |||||
| 2 | Tue | 29 Jan | Numbers & Arithmetic [] | 2.4, 3.2, A.2, A.5 & A.6 | Lab 1: Adder/Logisim intro | |||
| Thu | 31 Jan |
State [] Memory [] FSMs [] |
A.7, A.8 (up to register files), A.10, A.11 | |||||
| 3 | Tue | 5 Feb | A.8 (register files), A.9 | Lab 2: LeftShift32 | Project 1 + ALU | |||
| Thu | 7 Feb | Intro to RISC-V Processor [] | 2.1-3, 2.5-7, 2.19-20 | |||||
| 4 | Tue | 12 Feb | 4.1 - 4.4 | Lab 3: Basic CPU | C Assignment 1: Palindrome | |||
| Thu | 14 Feb | Pipelined RISC-V
[] Pipeline Hazards Control Hazards |
4.5-4.6 | |||||
| Fri | 15 Feb | Project 1 Due | ||||||
| 5 | Tue | 19 Feb | 4.7 | Lab 4: Circuit Minimization | Project 2 | Mini-RISC-V | |||
| Thu | 21 Feb | 4.8 | ||||||
| 6 | Tue | 26 Feb | Winter Break | Lab 5: Pipelining | ||||
| Thu | 28 Feb | Performance [] | 1.6 | Project 2: Design Doc, C Assignment 1 |
||||
| 7 | Tue | 5 Mar | RISC & CISC & ISA Variations [] | 2.16 - 2.18, & 2.21 | Lab 6: FSM | Prelim 1 | ||
| Thu | 7 Mar | Calling Conventions [] | 2.8 | |||||
| 8 | Mon | 11 Mar | Project 2 Due | |||||
| Tue | 12 Mar | Lab 7: Calling Conventions | Project 3 @ Fully-Pipelined RISC-V | |||||
| Thu | 14 Mar | Linkers [] | 2.12 | |||||
| 9 | Mon | 18 Mar | ||||||
| Tue | 19 Mar | Caches [] | 5.1-3 (except writes) | Lab 8 / C Lab 2: Selection Sort | ||||
| Thu | 21 Mar | 5.3-4, 5.8, 5.10, Also, 5.14 & 5.17 | ||||||
| Fri | 22 Mar | C Assignment 2: Tree Traversal | ||||||
| 10 | Tue | 26 Mar | Lab 9 / C Lab 3: Introduction to GDB | |||||
| Thu | 28 Mar | Virtual Memory 1 [] | 5.7 (up to TLBs) | Project 3 Due | ||||
| Tue | 2 Apr | Spring Break | ||||||
| Thu | 4 Apr | |||||||
| 11 | Tue | 9 Apr | Virtual Memory 2 | 5.7 | Lab 10 / C Lab 4: ArrayList | Project 4 > Buffer Overflow | ||
| Thu | 11 Apr | Traps/Exceptional Control Flow [] | 4.9, 5.14 | |||||
| 12 | Tue | 16 Apr | Multicore & Synchronization [] | 1.7, 1.8, 4.10, 5.10, 6.1-6.5 | Lab 11: Caches and Virtual Memory | Project 5 $ Caches | Project 4 Due | |
| Thu | 18 Apr | 2.11 | ||||||
| Fri | 19 Apr | C Assignment 2 Due | ||||||
| 13 | Tue | 23 Apr | Lab 12: First 5 Malloc Tests | |||||
| Thu | 25 Apr | 6.6 | ||||||
| Fri | 26 Apr | Project 5 Due | ||||||
| 14 | Tue | 30 Apr | I/O [] | 1.4 | Lab 13: Optional Lab (Prelim practice) | Project 6 * Malloc | ||
| Thu | 2 May | Storage [] | 5.2, 5.11, 5.18 | Prelim 2 | ||||
| 15 | Tue | 7 May | Future Directions | Project 6: Design Doc | ||||
| Thu | 9 May | |||||||
| 16 | Tue | 14 May | ||||||
| Thu | 16 May | Project 6 | ||||||
| 17 | Tue | 21 May | ||||||
| Thu | 23 May |