RISC-V ISA Reference

Instruction Encoding Templates

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R-type funct7 rs2 rs1 funct3 rd opcode
I-type imm[11:0]
S-Type imm[11:5] rs2 imm[4:0]
B-type imm[12|10:5] imm [4:1|11]
J-type imm[20|10:1|11|19:12] rd
U-type imm[31:12]

RV32I Base Integer Instruction Set

Arithmetic Instructions

Instruction Name Description Opcode Funct3 Funct7
R-type add rd rs1 rs2 ADD R[rd] = R[rs1] + R[rs2] 011 0011 000 000 0000
sub rd rs1 rs2 SUBTRACT R[rd] = R[rs1] - R[rs2] 011 0011 000 010 0000
and rd rs1 rs2 bitwise AND R[rd] = R[rs1] & R[rs2] 011 0011 111 000 0000
or rd rs1 rs2 bitwise OR R[rd] = R[rs1] | R[rs2] 011 0011 110 000 0000
xor rd rs1 rs2 bitwise XOR R[rd] = R[rs1] ^ R[rs2] 011 0011 100 000 0000
sll rd rs1 rs2 shift left logical R[rd] = R[rs1] << R[rs2] 011 0011 001 000 0000
srl rd rs1 rs2 shift right logical R[rd] = R[rs1] >> R[rs2]
(zero-extend)		 011 0011 101 000 0000
sra rd rs1 rs2 shift right arithmetic R[rd] = R[rs1] >> R[rs2]
(sign-extend)		 011 0011 101 010 0000
slt rd rs1 rs2 set less than (signed) if (R[rs1] < R[rs2]) { R[rd] = 1; } else { R[rd] = 0; } 011 0011 010 000 0000
sltu rd rs1 rs2 set less than (unsigned) 011 0011 011 000 0000
I-type addi rd rs1 imm ADD immediate R[rd] = R[rs1] + imm 011 0011 000
andi rd rs1 imm bitwise AND immediate R[rd] = R[rs1] & imm 011 0011 111
ori rd rs1 imm bitwise OR immediate R[rd] = R[rs1] | imm 011 0011 110
xori rd rs1 imm bitwise XOR immediate R[rd] = R[rs1] ^ imm 011 0011 100
slti rd rs1 imm set less than immediate (signed) if (R[rs1] < imm) { R[rd] = 1; } else { R[rd] = 0; } 001 0011 010
sltiu rd rs1 imm set less than immediate (unsigned) 001 0011 011
slli rd rs1 imm shift left logical immediate R[rd] = R[rs1] << imm 011 0011 001 000 0000
srli rd rs1 imm shift right logical immediate R[rd] = R[rs1] >> imm
(zero-extend)		 011 0011 101 000 0000
srai rd rs1 imm shift right arithmetic immediate R[rd] = R[rs1] >> imm
(sign-extend)		 011 0011 101 010 0000

Memory Instructions

Instruction Name Description Opcode Funct3
I-type lb rd imm(rs1) load byte R[rd] = M[R[rs1] + imm][7:0] 000 0011 000
lbu rd imm(rs1) load byte R[rd] = M[R[rs1] + imm][7:0]
(unsigned)		 000 0011 100
lh rd imm(rs1) load half-word R[rd] = M[R[rs1] + imm][15:0] 000 0011 001
lhu rd imm(rs1) load half-word R[rd] = M[R[rs1] + imm][15:0]
(unsigned)		 000 0011 101
lw rd imm(rs1) load word R[rd] = M[R[rs1] + imm][31:0] 000 0011 000
S-Type sb rs2 imm(rs1) store byte M[R[rs1] + imm][7:0] = R[rs2][7:0] 010 0011 000
sh rs2 imm(rs1) store half-word M[R[rs1] + imm][15:0] = R[rs2][15:0] 010 0011 001
sw rs2 imm(rs1) store word M[R[rs1] + imm][31:0] = R[rs2][31:0] 010 0011 010

Control Instructions

Instruction Name Description Opcode Funct3
B-type beq rs1 rs2 label branch if equal if (R[rs1] == R[rs2]) { PC = PC + offset } 011 0011 000
bne rs1 rs2 label branch if not equal if (R[rs1] != R[rs2]) { PC = PC + offset } 011 0011 000
blt rs1 rs2 label branch if less than (signed) if (R[rs1] < R[rs2]) { PC = PC + offset } 011 0011 000
bltu rs1 rs2 label branch if less than (unsigned) 011 0011 000
bge rs1 rs2 label branch if greater or equal (signed) if (R[rs1] >= R[rs2]) { PC = PC + offset } 011 0011 000
bgeu rs1 rs2 label branch if greater or equal (unsigned) 011 0011 000
J-type jal rd label jump and link R[rd] = PC + 4 PC = PC + offset 110 1111
I-type jalr rd rs1 label jump and link register R[rd] = PC + 4 PC = R[rs1] + imm 110 0111 000

Other Instructions

Instruction Name Description Opcode Funct3
U-type auipc rd immu add upper immediate to PC imm = immu << 12 R[rd] = PC + imm 011 0111
lui rd immu load upper immediate imm = immu << 12 R[rd] = imm 001 0111
I-type ebreak environment BREAK asks the debugger to do something (imm = 0) 111 0011 000
ecall environment ECALL asks the OS to do something (imm = 1) 111 0011 000

TODO:

Pseudo-Instructions

ISA Extensions? (in particular, mul)

RV64I Base Integer Instruction Set

RV32A Extension for Atomic Instructions