Team Members
- Ghurye Sourabh Sunil - 130050001
- Nikhil Vyas - 130050023
- Utkarsh Mall - 130050037
- Mayank Sahu - 130050038
- Nitesh Dudhey - 130050039
Objective
- Designed and simulated Universal Asynchronous Receiver/Transmitter circuit(UART) in Xilinx ISE.
- Implement the simulated design on ATLYS board.
- Used Finite State Machines while implementing UART.
Instructions
- Extract the 'UART.zip' file in working directory.
- Open '.xise' file of the project with ISE tool.
- For testing purposes use the code as it is.
- Load source on ATLYS board and run it using TERATERM over a PC.
- For working purposes open 'UART_top.vhd', make changes as written in comments, and load again on ATLYS board.
Presentation