Preventing Glitches and Short Circuits in High-Level Self-Timed Chip Specifications
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Preventing Glitches and Short Circuits in High-Level Self-Timed Chip Specifications

PLDI 2015: [pdf] [bibtex] [artifact]

Authors: Stephen Longfield, Brittany Nkounkou, Rajit Manohar, and Ross Tate

Abstract

Self-timed chip designs are commonly specified in a high-level message-passing language called CHP. This language is closely related to Hoare's CSP except it admits erroneous behavior due to the necessary limitations of efficient hardware implementations. For example, two processes sending on the same channel at the same time causes glitches and short circuits in the physical chip implementation. If a CHP program maintains certain invariants, such as only one process is sending on any given channel at a time, it can guarantee an error-free execution that behaves much like a CSP program would. In this paper, we present an inferable effect system for ensuring that these invariants hold, drawing from model-checking methodologies while exploiting language-usage patterns and domain-specific specializations to achieve efficiency. This analysis is sound, and is even complete for the common subset of CHP programs without data-sensitive synchronization. We have implemented the analysis and demonstrated that it scales to validate even microprocessors.

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