Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx45
Project ID (random number) f5208b875d9441b6937ec6ae79c0c137.D02C832437F84A0CA4589DA5D91F1A77.4 Target Package: csg324
Registration ID 211001458_0_0_018 Target Speed: -3
Date Generated 2015-04-30T22:38:00 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 1696 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 1696 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 4-bit adder=2
 Counters=3
  • 3-bit up counter=2
  • 8-bit up counter=1
 FSMs=2 Multiplexers=18
  • 1-bit 2-to-1 multiplexer=9
  • 1-bit 8-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=5
  • 4-bit 3-to-1 multiplexer=1
  • 8-bit 2-to-1 multiplexer=2
 Registers=38
  • Flip-Flops=38
 		MiscellaneousStatistics
  • AGG_BONDED_IO=4
  • AGG_IO=4
  • AGG_LOCED_IO=4
  • AGG_SLICE=20
  • NUM_BONDED_IOB=4
  • NUM_BSFULL=46
  • NUM_BSLUTONLY=23
  • NUM_BSREGONLY=1
  • NUM_BSUSED=70
  • NUM_BUFG=2
  • NUM_LOCED_IOB=4
  • NUM_LOGIC_O5ANDO6=15
  • NUM_LOGIC_O5ONLY=6
  • NUM_LOGIC_O6ONLY=47
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=6
  • NUM_SLICEL=2
  • NUM_SLICEX=18
  • NUM_SLICE_CARRY4=2
  • NUM_SLICE_CONTROLSET=6
  • NUM_SLICE_CYINIT=91
  • NUM_SLICE_FF=56
  • NUM_SLICE_UNUSEDCTRL=3
  • NUM_UNUSABLE_FF_BELS=24
 		NetStatistics
  • NumNets_Active=94
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=9
  • NumNodesOfType_Active_BOUNCEIN=13
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=17
  • NumNodesOfType_Active_CLKPINFEED=6
  • NumNodesOfType_Active_CNTRLPIN=13
  • NumNodesOfType_Active_DOUBLE=86
  • NumNodesOfType_Active_GENERIC=6
  • NumNodesOfType_Active_GLOBAL=23
  • NumNodesOfType_Active_INPUT=3
  • NumNodesOfType_Active_IOBIN2OUT=3
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_LUTINPUT=293
  • NumNodesOfType_Active_OUTBOUND=89
  • NumNodesOfType_Active_OUTPUT=90
  • NumNodesOfType_Active_PADINPUT=1
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=60
  • NumNodesOfType_Active_PINFEED=323
  • NumNodesOfType_Active_QUAD=32
  • NumNodesOfType_Active_REGINPUT=1
  • NumNodesOfType_Active_SINGLE=149
  • NumNodesOfType_Vcc_HVCCOUT=8
  • NumNodesOfType_Vcc_LUTINPUT=21
  • NumNodesOfType_Vcc_PINFEED=21
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=2
  • IOB-IOBS=2
  • SLICEL-SLICEM=2
  • SLICEX-SLICEL=6
  • SLICEX-SLICEM=2
 		SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=2
  • FF_SR=11
  • HARD0=1
  • IOB=4
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=1
  • LUT5=21
  • LUT6=69
  • PAD=4
  • REG_SR=45
  • SLICEL=2
  • SLICEX=18
 
Configuration Data
FF_SR
  • CK=[CK:11] [CK_INV:0]
  • SRINIT=[SRINIT0:11]
  • SYNC_ATTR=[ASYNC:1] [SYNC:10]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:1]
  • SLEW=[SLOW:1]
  • SUSPEND=[3STATE:1]
 REG_SR
  • CK=[CK:45] [CK_INV:0]
  • LATCH_OR_FF=[FF:45]
  • SRINIT=[SRINIT0:37] [SRINIT1:8]
  • SYNC_ATTR=[ASYNC:22] [SYNC:23]
 SLICEX
  • CLK=[CLK:17] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=1
  • CO3=1
  • CYINIT=1
  • DI0=2
  • DI1=2
  • DI2=2
  • DI3=1
  • O0=2
  • O1=2
  • O2=2
  • O3=2
  • S0=2
  • S1=2
  • S2=2
  • S3=2
 FF_SR
  • CE=2
  • CK=11
  • D=11
  • Q=11
  • SR=10
 HARD0
  • 0=1
 IOB
  • I=3
  • O=1
  • PAD=4
 IOB_IMUX
  • I=3
  • OUT=3
 IOB_INBUF
  • OUT=3
  • PAD=3
 IOB_OUTBUF
  • IN=1
  • OUT=1
 LUT5
  • A1=4
  • A2=12
  • A3=12
  • A4=10
  • A5=9
  • O5=21
 LUT6
  • A1=32
  • A2=36
  • A3=45
  • A4=50
  • A5=68
  • A6=69
  • O6=69
 PAD
  • PAD=4
 REG_SR
  • CE=13
  • CK=45
  • D=45
  • Q=45
  • SR=23
 SLICEL
  • A5=2
  • A6=2
  • AMUX=2
  • B5=2
  • B6=2
  • BMUX=2
  • C5=2
  • C6=2
  • CIN=1
  • CMUX=2
  • COUT=1
  • D5=1
  • D6=2
  • DMUX=2
 SLICEX
  • A=2
  • A1=9
  • A2=11
  • A3=13
  • A4=14
  • A5=16
  • A6=16
  • AMUX=4
  • AQ=15
  • AX=1
  • B=4
  • B1=9
  • B2=12
  • B3=12
  • B4=12
  • B5=16
  • B6=16
  • BMUX=4
  • BQ=12
  • C=8
  • C1=11
  • C2=12
  • C3=14
  • C4=14
  • C5=16
  • C6=16
  • CE=4
  • CLK=17
  • CMUX=3
  • CQ=8
  • D=3
  • D1=6
  • D2=9
  • D3=9
  • D4=10
  • D5=13
  • D6=13
  • DMUX=3
  • DQ=10
  • SR=9
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
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  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 26 24 0 0 0 0 0
bitgen 20 20 0 0 0 0 0
map 22 22 0 0 0 0 0
netgen 7 7 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 23 23 0 0 0 0 0
par 22 22 0 0 0 0 0
trce 22 22 0 0 0 0 0
xst 294 294 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/sse_db_obj_prop_attributes.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/UART_TB PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2015-04-13T15:25:53 PROP_intWbtProjectID=D02C832437F84A0CA4589DA5D91F1A77
PROP_intWbtProjectIteration=4 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.UART_TB PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx45 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VHDL=8
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=19 NGDBUILD_NUM_FDE=4
NGDBUILD_NUM_FDR=22 NGDBUILD_NUM_FDRE=11 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=7 NGDBUILD_NUM_LUT2=16 NGDBUILD_NUM_LUT3=15
NGDBUILD_NUM_LUT4=10 NGDBUILD_NUM_LUT5=3 NGDBUILD_NUM_LUT6=31 NGDBUILD_NUM_MUXCY=7
NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=8
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=19 NGDBUILD_NUM_FDE=4 NGDBUILD_NUM_FDR=22
NGDBUILD_NUM_FDRE=11 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=7 NGDBUILD_NUM_LUT2=16 NGDBUILD_NUM_LUT3=15
NGDBUILD_NUM_LUT4=10 NGDBUILD_NUM_LUT5=3 NGDBUILD_NUM_LUT6=31 NGDBUILD_NUM_MUXCY=7
NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=8
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx45-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=499 ms, 32108 KB
Total Signals=8
Total Nets=12
Total Blocks=5
Total Processes=3
Total Simulation Time=1 us
Simulation Resource Usage=0.046875 sec, 336408 KB
Simulation Mode=gui
Hardware CoSim=0