MIPSI is an instruction-level simulator for the MIPS family of processors. Its main attributes are simplicity and robustness - mipsi can run SPEC benchmarks as well as complicated, on-the-fly code generating programs such as the Standard ML of New Jersey without any modification. MIPSI runs on big or little endian MIPS boxes and on Alpha platforms. On mips based work stations, the slowdown due to simulation is about 65 times the speed of native code for most SPEC benchmarks. On an alpha 400 cross-simulating an R3000, the slowdown is roughly 4.
My goal in writing MIPSI was to investigate the amount of fine-grain instruction level parallelism available in C and ML programs, and then to find out if alternative garbage collection schemes could possibly increase the amount of parallelism. The garbage collector is responsible for the layout of data in garbage collected systems. Thus the decisions made by the garbage collector have a big impact on the cache performance of programs. On future architectures with speculative execution, such impact is amplified as the speculative forward progress of the processor is interrupted by cache misses.
More than 400 research projects have adopted MIPSI. Here is a sampling:
Dean Tullsen, Susan Eggers and Hank Levy have modified MIPSI to simulate the Alpha processor in order to investigate multithreaded processor architectures. This work is now known as Simultaneous Multithreading. Dean's simulator, based on some MIPSI code, is now used at Intel.
Andrew Appel and Marcelo Goncalves at Princeton University have used MIPSI to investigate garbage collection alternatives for future architectures. Marcelo used MIPSI for simulations that appeared in his thesis.
This paper on the Structure and Performance of Interpreters has examined the runtime behavior of the MIPSI simulator in detail.
MIPSI requires Digital Unix on alpha processors and DEC Ultrix on MIPS processors. It can also be compiled and executed on an SGI Irix with a minimal amount of effort. If you are interested in porting MIPSI, let me know and I would be glad to help.
MIPSI is an instruction level simulator. The internal operation of the MIPS chip below the cycle level is not simulated in order not to sacrifice performance.
MIPSI simulates the floating point instructions as well as arithmetic over/underflows, NANs and divide by zero exceptions at the signal level and reflects them to the simulated program in the same manner as the underlying operating system. It does not simulate interrupts or any I/O devices.
By all means. Email me and we will pick the most expedient route to folding your changes into MIPSI.