<article>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#article09_11_19_1845205</id>
	<title>Building a 32-Bit, One-Instruction Computer</title>
	<author>timothy</author>
	<datestamp>1258657920000</datestamp>
	<htmltext><a href="http://hughpickens.com/" rel="nofollow">Hugh Pickens</a> writes <i>"The advantages of RISC are well known &mdash; simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution. Al Williams writes in Dr Dobbs about taking RISC to its logical conclusion by <a href="http://www.ddj.com/embedded/221800122?cid=RSSfeed\_DDJ\_All">designing a functional computer called One-Der with only a single simple instruction</a> &mdash; a 32-bit Transfer Triggered Architecture (TTA) CPU that operates at roughly 10 MIPS. 'When I tell this story in person, people are usually squirming with the inevitable question: What's the one instruction?' writes Williams. 'It turns out there's several ways to construct a single instruction CPU, but the method I had stumbled on does everything via a move instruction (hence the name, "<a href="http://en.wikipedia.org/wiki/One\_instruction\_set\_computer#Triggered\_Move">Transfer Triggered Architecture</a>").' The CPU is implemented on a Field Programmable Gate Array (FPGA) device and the prototype works on a <a href="http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,799&amp;Prod=S3BOARD">'Spartan 3 Starter Board' with an XS3C1000 device available from Digilent</a> that has the equivalent of about 1,000,000 logic gates, costing between $100 and $200. 'Applications that can benefit from custom instruction in hardware &mdash; things like digital signal processing, for example &mdash; are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU.'"</i></htmltext>
<tokenext>Hugh Pickens writes " The advantages of RISC are well known    simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds , more registers , and pipelining to provide the appearance of single-cycle execution .
Al Williams writes in Dr Dobbs about taking RISC to its logical conclusion by designing a functional computer called One-Der with only a single simple instruction    a 32-bit Transfer Triggered Architecture ( TTA ) CPU that operates at roughly 10 MIPS .
'When I tell this story in person , people are usually squirming with the inevitable question : What 's the one instruction ?
' writes Williams .
'It turns out there 's several ways to construct a single instruction CPU , but the method I had stumbled on does everything via a move instruction ( hence the name , " Transfer Triggered Architecture " ) .
' The CPU is implemented on a Field Programmable Gate Array ( FPGA ) device and the prototype works on a 'Spartan 3 Starter Board ' with an XS3C1000 device available from Digilent that has the equivalent of about 1,000,000 logic gates , costing between $ 100 and $ 200 .
'Applications that can benefit from custom instruction in hardware    things like digital signal processing , for example    are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU .
' "</tokentext>
<sentencetext>Hugh Pickens writes "The advantages of RISC are well known — simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution.
Al Williams writes in Dr Dobbs about taking RISC to its logical conclusion by designing a functional computer called One-Der with only a single simple instruction — a 32-bit Transfer Triggered Architecture (TTA) CPU that operates at roughly 10 MIPS.
'When I tell this story in person, people are usually squirming with the inevitable question: What's the one instruction?
' writes Williams.
'It turns out there's several ways to construct a single instruction CPU, but the method I had stumbled on does everything via a move instruction (hence the name, "Transfer Triggered Architecture").
' The CPU is implemented on a Field Programmable Gate Array (FPGA) device and the prototype works on a 'Spartan 3 Starter Board' with an XS3C1000 device available from Digilent that has the equivalent of about 1,000,000 logic gates, costing between $100 and $200.
'Applications that can benefit from custom instruction in hardware — things like digital signal processing, for example — are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU.
'"</sentencetext>
</article>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161716</id>
	<title>It's obvious</title>
	<author>SnarfQuest</author>
	<datestamp>1258662960000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>The instruction is "What is 7 times 9"</p></htmltext>
<tokenext>The instruction is " What is 7 times 9 "</tokentext>
<sentencetext>The instruction is "What is 7 times 9"</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168336</id>
	<title>Re:Not new, and not too useful</title>
	<author>wd5gnr</author>
	<datestamp>1258654680000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Actually, a few points:
1) Yes it is an old idea. The article points out a few links to MOVE, MAXQ, and Wikipedia about it.
2) The assembler is there that does macro like CALL, PUSH, etc. Its actually an interesting piece in of itself since it converts assembly to C macros and then uses gcc to drive the output.
3) The board has a 1M gate FPGA but the CPU doesn't use anywhere near all of it, but you can't get an FPGA with exactly the gate count you need (gate count is deceptive anyway). And much of what it does use is for onboard "block RAM" to make it a SOC. Go with external memory for program and data and the gate count drops sharply. Oh and Novix was a 16 bit CPU with no onboard memory, so that's kind of an apple and orange comparison. You can reduce the gate count by dropping unused FUs too.

The CPU as presented actually does shifting and a host of other operations in one cycle. The DDJ version does not do hardware multiply or divide but it is easy to add that or any other operation you might want.</htmltext>
<tokenext>Actually , a few points : 1 ) Yes it is an old idea .
The article points out a few links to MOVE , MAXQ , and Wikipedia about it .
2 ) The assembler is there that does macro like CALL , PUSH , etc .
Its actually an interesting piece in of itself since it converts assembly to C macros and then uses gcc to drive the output .
3 ) The board has a 1M gate FPGA but the CPU does n't use anywhere near all of it , but you ca n't get an FPGA with exactly the gate count you need ( gate count is deceptive anyway ) .
And much of what it does use is for onboard " block RAM " to make it a SOC .
Go with external memory for program and data and the gate count drops sharply .
Oh and Novix was a 16 bit CPU with no onboard memory , so that 's kind of an apple and orange comparison .
You can reduce the gate count by dropping unused FUs too .
The CPU as presented actually does shifting and a host of other operations in one cycle .
The DDJ version does not do hardware multiply or divide but it is easy to add that or any other operation you might want .</tokentext>
<sentencetext>Actually, a few points:
1) Yes it is an old idea.
The article points out a few links to MOVE, MAXQ, and Wikipedia about it.
2) The assembler is there that does macro like CALL, PUSH, etc.
Its actually an interesting piece in of itself since it converts assembly to C macros and then uses gcc to drive the output.
3) The board has a 1M gate FPGA but the CPU doesn't use anywhere near all of it, but you can't get an FPGA with exactly the gate count you need (gate count is deceptive anyway).
And much of what it does use is for onboard "block RAM" to make it a SOC.
Go with external memory for program and data and the gate count drops sharply.
Oh and Novix was a 16 bit CPU with no onboard memory, so that's kind of an apple and orange comparison.
You can reduce the gate count by dropping unused FUs too.
The CPU as presented actually does shifting and a host of other operations in one cycle.
The DDJ version does not do hardware multiply or divide but it is easy to add that or any other operation you might want.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161782</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30165928</id>
	<title>Creating a one-intsruction computer is easy</title>
	<author>Anonymous</author>
	<datestamp>1258634400000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Even a child can create a one-instruction computer, as long as the instruction is "nop."</p></htmltext>
<tokenext>Even a child can create a one-instruction computer , as long as the instruction is " nop .
"</tokentext>
<sentencetext>Even a child can create a one-instruction computer, as long as the instruction is "nop.
"</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162054</id>
	<title>Fastest Processor</title>
	<author>Anonymous</author>
	<datestamp>1258664100000</datestamp>
	<modclass>None</modclass>
	<modscore>-1</modscore>
	<htmltext><p>I have built the fastest processor in the world using this technique.  Its one instruction is NOP.  It does nothing faster than anything else on the planet.</p></htmltext>
<tokenext>I have built the fastest processor in the world using this technique .
Its one instruction is NOP .
It does nothing faster than anything else on the planet .</tokentext>
<sentencetext>I have built the fastest processor in the world using this technique.
Its one instruction is NOP.
It does nothing faster than anything else on the planet.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161612</id>
	<title>So old it's new.</title>
	<author>LaminatorX</author>
	<datestamp>1258662660000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>5</modscore>
	<htmltext><p>Sounds a hell of a lot like the read/write head of the Turing Machine to me.</p></htmltext>
<tokenext>Sounds a hell of a lot like the read/write head of the Turing Machine to me .</tokentext>
<sentencetext>Sounds a hell of a lot like the read/write head of the Turing Machine to me.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164676</id>
	<title>Re:That instruction is ..........</title>
	<author>ajs</author>
	<datestamp>1258629000000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><div class="quote"><p>It's got only one instruction.<nobr> <wbr></nobr>...and the first parameter to that instruction controls what the instruction does with the rest of the parameters.</p><p>(p.s. I wish this was just a joke, but this is pretty much what it seems to be doing)</p></div><p>Yep, the one instruction is a store (I think he needs a load too, but I guess you could get around that by self-modifying).</p><p>You'll just have to prefix all instructions with "STORE" as all other instructions will be accumulators rather than instructions. Of course, this makes pipelining more complex, but nothing else really changes.</p></div>
	</htmltext>
<tokenext>It 's got only one instruction .
...and the first parameter to that instruction controls what the instruction does with the rest of the parameters. ( p.s .
I wish this was just a joke , but this is pretty much what it seems to be doing ) Yep , the one instruction is a store ( I think he needs a load too , but I guess you could get around that by self-modifying ) .You 'll just have to prefix all instructions with " STORE " as all other instructions will be accumulators rather than instructions .
Of course , this makes pipelining more complex , but nothing else really changes .</tokentext>
<sentencetext>It's got only one instruction.
...and the first parameter to that instruction controls what the instruction does with the rest of the parameters.(p.s.
I wish this was just a joke, but this is pretty much what it seems to be doing)Yep, the one instruction is a store (I think he needs a load too, but I guess you could get around that by self-modifying).You'll just have to prefix all instructions with "STORE" as all other instructions will be accumulators rather than instructions.
Of course, this makes pipelining more complex, but nothing else really changes.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162106</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164910</id>
	<title>Oh my, you'll never believe what I'm about to say</title>
	<author>stonewolf</author>
	<datestamp>1258630020000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>4</modscore>
	<htmltext><p> A cousin of mine (Howdy Rusty!) described this concept to me in the '70s while I was taking classes toward my CS degree.</p><p>A little background: I went to the good old University of Utah which had a Boroughs 1700 with user writable microcode and so a lot of project centered around writing microcode and designing micro architectures. A friend was trying to code up a single instruction machine based on Curry Combinators. I thought he was nuts, but I liked the idea of a single instruction machine. So, I was talking to my cousin and he described an architecture that had one instruction that was a source and a destination address. Any address could be either memory or a register in a functional unit, an FU for short. No kidding, that is how he described it.</p><p>The only trouble was trying to figure out how to do a conditional branch.</p><p>A few years later while I was in gradual school I solved that problem and wrote paper about it. Being a gradual student I could not publish without permission from my adviser. Well, he got a good laugh out of the idea and told me not to show it to anyone. So, of course I sent it to everyone I knew. They all had a good laugh to. Said it was the funniest thing I had ever written. You see, I was into writing humorous stories at the time and people thought this was another one. Oh well, I have a print out of the thing around here somewhere.</p><p>What I really liked about the architecture is that if you started modifying it to make it more economical, doing things like making the addresses have different lengths and adding a bit to tell you if the long address is the source or the destination, the move architecture starts looking more and more like a classic instruction set architecture. I thought that was very cool. When you look at micro coded architectures and think about a pure move based processor it really does look like all traditional architectures are attempts to make the one instruction machine make more economical use of instruction bits.</p><p>So, how did I solve the conditional branch problem? Pretty much the way this fellow did. Every FU may, or may not, cause condition flags to be set. I added registers where you could read and write the condition bits and read and write the program counter. I also added a mask register that was anded with the condition register so you could enable and disable conditions. Then I just made the current instruction conditional on the values of the flags register anded with the mask register. If the result was non-zero the current instruction was skipped. Of course, the machine had to clear the condition register after each instruction was executed. (Hmm, it would make more sense to only make moves to the program counter conditional and it would make more sense to only clear the flags after a move to the instructions counter... Hey was a gradual student back then!<nobr> <wbr></nobr>:) That approach allowed you to select say the sign bit from one ALU, do an subtraction by moving values to two registers in the ALU, then jump if the sign bit is set. It also let you directly make any instruction conditional so you could implement something like the ABS() function without any jumps. Or, at least that was the idea.</p><p>I called my one instruction: The Conditional Move From Here To There And Clear Flags, or TCMFHTTACF insturction. The assembly for it was really dull, it just always had the same op code down the left hand edge of the screen... Ok, really, I just never listed anything but addresses when I wrote code for it.</p><p>Nice to see that someone actually built one of these. BTW, this kind of architecture makes it easy to add multiple execution units. With parallel execution and careful use of shared and private FUs and memories you can build a pretty damn powerful special purpose processor without a lot of hardware complexity.</p><p>This just to damn cool... someone finally built it!</p><p>Stonewolf</p></htmltext>
<tokenext>A cousin of mine ( Howdy Rusty !
) described this concept to me in the '70s while I was taking classes toward my CS degree.A little background : I went to the good old University of Utah which had a Boroughs 1700 with user writable microcode and so a lot of project centered around writing microcode and designing micro architectures .
A friend was trying to code up a single instruction machine based on Curry Combinators .
I thought he was nuts , but I liked the idea of a single instruction machine .
So , I was talking to my cousin and he described an architecture that had one instruction that was a source and a destination address .
Any address could be either memory or a register in a functional unit , an FU for short .
No kidding , that is how he described it.The only trouble was trying to figure out how to do a conditional branch.A few years later while I was in gradual school I solved that problem and wrote paper about it .
Being a gradual student I could not publish without permission from my adviser .
Well , he got a good laugh out of the idea and told me not to show it to anyone .
So , of course I sent it to everyone I knew .
They all had a good laugh to .
Said it was the funniest thing I had ever written .
You see , I was into writing humorous stories at the time and people thought this was another one .
Oh well , I have a print out of the thing around here somewhere.What I really liked about the architecture is that if you started modifying it to make it more economical , doing things like making the addresses have different lengths and adding a bit to tell you if the long address is the source or the destination , the move architecture starts looking more and more like a classic instruction set architecture .
I thought that was very cool .
When you look at micro coded architectures and think about a pure move based processor it really does look like all traditional architectures are attempts to make the one instruction machine make more economical use of instruction bits.So , how did I solve the conditional branch problem ?
Pretty much the way this fellow did .
Every FU may , or may not , cause condition flags to be set .
I added registers where you could read and write the condition bits and read and write the program counter .
I also added a mask register that was anded with the condition register so you could enable and disable conditions .
Then I just made the current instruction conditional on the values of the flags register anded with the mask register .
If the result was non-zero the current instruction was skipped .
Of course , the machine had to clear the condition register after each instruction was executed .
( Hmm , it would make more sense to only make moves to the program counter conditional and it would make more sense to only clear the flags after a move to the instructions counter... Hey was a gradual student back then !
: ) That approach allowed you to select say the sign bit from one ALU , do an subtraction by moving values to two registers in the ALU , then jump if the sign bit is set .
It also let you directly make any instruction conditional so you could implement something like the ABS ( ) function without any jumps .
Or , at least that was the idea.I called my one instruction : The Conditional Move From Here To There And Clear Flags , or TCMFHTTACF insturction .
The assembly for it was really dull , it just always had the same op code down the left hand edge of the screen... Ok , really , I just never listed anything but addresses when I wrote code for it.Nice to see that someone actually built one of these .
BTW , this kind of architecture makes it easy to add multiple execution units .
With parallel execution and careful use of shared and private FUs and memories you can build a pretty damn powerful special purpose processor without a lot of hardware complexity.This just to damn cool... someone finally built it ! Stonewolf</tokentext>
<sentencetext> A cousin of mine (Howdy Rusty!
) described this concept to me in the '70s while I was taking classes toward my CS degree.A little background: I went to the good old University of Utah which had a Boroughs 1700 with user writable microcode and so a lot of project centered around writing microcode and designing micro architectures.
A friend was trying to code up a single instruction machine based on Curry Combinators.
I thought he was nuts, but I liked the idea of a single instruction machine.
So, I was talking to my cousin and he described an architecture that had one instruction that was a source and a destination address.
Any address could be either memory or a register in a functional unit, an FU for short.
No kidding, that is how he described it.The only trouble was trying to figure out how to do a conditional branch.A few years later while I was in gradual school I solved that problem and wrote paper about it.
Being a gradual student I could not publish without permission from my adviser.
Well, he got a good laugh out of the idea and told me not to show it to anyone.
So, of course I sent it to everyone I knew.
They all had a good laugh to.
Said it was the funniest thing I had ever written.
You see, I was into writing humorous stories at the time and people thought this was another one.
Oh well, I have a print out of the thing around here somewhere.What I really liked about the architecture is that if you started modifying it to make it more economical, doing things like making the addresses have different lengths and adding a bit to tell you if the long address is the source or the destination, the move architecture starts looking more and more like a classic instruction set architecture.
I thought that was very cool.
When you look at micro coded architectures and think about a pure move based processor it really does look like all traditional architectures are attempts to make the one instruction machine make more economical use of instruction bits.So, how did I solve the conditional branch problem?
Pretty much the way this fellow did.
Every FU may, or may not, cause condition flags to be set.
I added registers where you could read and write the condition bits and read and write the program counter.
I also added a mask register that was anded with the condition register so you could enable and disable conditions.
Then I just made the current instruction conditional on the values of the flags register anded with the mask register.
If the result was non-zero the current instruction was skipped.
Of course, the machine had to clear the condition register after each instruction was executed.
(Hmm, it would make more sense to only make moves to the program counter conditional and it would make more sense to only clear the flags after a move to the instructions counter... Hey was a gradual student back then!
:) That approach allowed you to select say the sign bit from one ALU, do an subtraction by moving values to two registers in the ALU, then jump if the sign bit is set.
It also let you directly make any instruction conditional so you could implement something like the ABS() function without any jumps.
Or, at least that was the idea.I called my one instruction: The Conditional Move From Here To There And Clear Flags, or TCMFHTTACF insturction.
The assembly for it was really dull, it just always had the same op code down the left hand edge of the screen... Ok, really, I just never listed anything but addresses when I wrote code for it.Nice to see that someone actually built one of these.
BTW, this kind of architecture makes it easy to add multiple execution units.
With parallel execution and careful use of shared and private FUs and memories you can build a pretty damn powerful special purpose processor without a lot of hardware complexity.This just to damn cool... someone finally built it!Stonewolf</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166010</id>
	<title>Re:RISC vs CISC - sigh</title>
	<author>RzUpAnmsCwrds</author>
	<datestamp>1258634760000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Right, I personally despise the term "RISC" because it conflates a number of architecture aspects.</p><p>Does RISC mean few instructions? If so, how do you explain modern PowerPC CPUs, which have a full set of vector, floating-point, and other instructions?</p><p>Does RISC mean load-store (most instructions only support register direct and immediate addressing)?</p><p>Does RISC mean pipelined?</p><p>There are pipelined CISC CPUs, there are CISC CPUs with fewer instructions than RISC CPUs, and there are "RISC" CPUs that aren't load-store.</p></htmltext>
<tokenext>Right , I personally despise the term " RISC " because it conflates a number of architecture aspects.Does RISC mean few instructions ?
If so , how do you explain modern PowerPC CPUs , which have a full set of vector , floating-point , and other instructions ? Does RISC mean load-store ( most instructions only support register direct and immediate addressing ) ? Does RISC mean pipelined ? There are pipelined CISC CPUs , there are CISC CPUs with fewer instructions than RISC CPUs , and there are " RISC " CPUs that are n't load-store .</tokentext>
<sentencetext>Right, I personally despise the term "RISC" because it conflates a number of architecture aspects.Does RISC mean few instructions?
If so, how do you explain modern PowerPC CPUs, which have a full set of vector, floating-point, and other instructions?Does RISC mean load-store (most instructions only support register direct and immediate addressing)?Does RISC mean pipelined?There are pipelined CISC CPUs, there are CISC CPUs with fewer instructions than RISC CPUs, and there are "RISC" CPUs that aren't load-store.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161790</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163226</id>
	<title>This machine has been around already!</title>
	<author>Anonymous</author>
	<datestamp>1258624740000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>My 32-bit one command machine just needs Start. It's that big button on the bottom left. Been around since '95. There's a even a Stones song for it!</p></htmltext>
<tokenext>My 32-bit one command machine just needs Start .
It 's that big button on the bottom left .
Been around since '95 .
There 's a even a Stones song for it !</tokentext>
<sentencetext>My 32-bit one command machine just needs Start.
It's that big button on the bottom left.
Been around since '95.
There's a even a Stones song for it!</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30165004</id>
	<title>Re:GOTO ...</title>
	<author>ciaran.mchale</author>
	<datestamp>1258630440000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><div class="quote"><p>I vote for GOTO as the only instruction.<br>
That would be hilarious.</p></div><p>Actually, GOTO would be considered harmful.</p></div>
	</htmltext>
<tokenext>I vote for GOTO as the only instruction .
That would be hilarious.Actually , GOTO would be considered harmful .</tokentext>
<sentencetext>I vote for GOTO as the only instruction.
That would be hilarious.Actually, GOTO would be considered harmful.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362</id>
	<title>"ideal for One-Der"?</title>
	<author>Anonymous</author>
	<datestamp>1258661880000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>4</modscore>
	<htmltext>It seems specious to say that One-Der is optimal for a task because it offers the flexibility of the underlying FPGA hardware.  If you have the FPGA hardware present to run the One-Der implementation, then you could just configure a more optimally designed processor out of it for whatever task you are actually performing.</htmltext>
<tokenext>It seems specious to say that One-Der is optimal for a task because it offers the flexibility of the underlying FPGA hardware .
If you have the FPGA hardware present to run the One-Der implementation , then you could just configure a more optimally designed processor out of it for whatever task you are actually performing .</tokentext>
<sentencetext>It seems specious to say that One-Der is optimal for a task because it offers the flexibility of the underlying FPGA hardware.
If you have the FPGA hardware present to run the One-Der implementation, then you could just configure a more optimally designed processor out of it for whatever task you are actually performing.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162868</id>
	<title>Re:Cheating?</title>
	<author>Anonymous</author>
	<datestamp>1258623660000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>No, it strikes me as "exposing the microcode" in a conventional CPU. And the way it is like a address bus would make it easy to add or delete instructions even on the fly.</p></htmltext>
<tokenext>No , it strikes me as " exposing the microcode " in a conventional CPU .
And the way it is like a address bus would make it easy to add or delete instructions even on the fly .</tokentext>
<sentencetext>No, it strikes me as "exposing the microcode" in a conventional CPU.
And the way it is like a address bus would make it easy to add or delete instructions even on the fly.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161416</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163750</id>
	<title>Re:Cheating?</title>
	<author>Anonymous</author>
	<datestamp>1258626240000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>A move is one instruction, two operations. Some processors have multiply-accumulate instruction that does two sequential operations. 68k and ARM have instructions that load/stores a number of registers with up to 8 or 16 operations per instruction. X86 have instructions that moves an arbitrary (limited by addressable range) number of bytes/words or double-words, up to 2^32 or 2^64 operations per instruction.</p><p>By implying that the size of an instruction depends on "multiple modes", isn't every instruction in a ordinary processor potentially the size as all architectural state? Or in a Internet connected machine the state of every connected machine, or even the state of the universe given that some of the machines could be connected to telescopes or other sensors?</p><p>So yes, it's a matter of definition.</p></htmltext>
<tokenext>A move is one instruction , two operations .
Some processors have multiply-accumulate instruction that does two sequential operations .
68k and ARM have instructions that load/stores a number of registers with up to 8 or 16 operations per instruction .
X86 have instructions that moves an arbitrary ( limited by addressable range ) number of bytes/words or double-words , up to 2 ^ 32 or 2 ^ 64 operations per instruction.By implying that the size of an instruction depends on " multiple modes " , is n't every instruction in a ordinary processor potentially the size as all architectural state ?
Or in a Internet connected machine the state of every connected machine , or even the state of the universe given that some of the machines could be connected to telescopes or other sensors ? So yes , it 's a matter of definition .</tokentext>
<sentencetext>A move is one instruction, two operations.
Some processors have multiply-accumulate instruction that does two sequential operations.
68k and ARM have instructions that load/stores a number of registers with up to 8 or 16 operations per instruction.
X86 have instructions that moves an arbitrary (limited by addressable range) number of bytes/words or double-words, up to 2^32 or 2^64 operations per instruction.By implying that the size of an instruction depends on "multiple modes", isn't every instruction in a ordinary processor potentially the size as all architectural state?
Or in a Internet connected machine the state of every connected machine, or even the state of the universe given that some of the machines could be connected to telescopes or other sensors?So yes, it's a matter of definition.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161416</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161646</id>
	<title>This FP f0r GNAA</title>
	<author>Anonymous</author>
	<datestamp>1258662780000</datestamp>
	<modclass>Offtopic</modclass>
	<modscore>-1</modscore>
	<htmltext><A HREF="http://goat.cx/" title="goat.cx" rel="nofollow">WWOT? the deve7oper</a> [goat.cx]</htmltext>
<tokenext>WWOT ?
the deve7oper [ goat.cx ]</tokentext>
<sentencetext>WWOT?
the deve7oper [goat.cx]</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161974</id>
	<title>Re:That instruction is ..........</title>
	<author>LowlyWorm</author>
	<datestamp>1258663740000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>No, it needs a two button keyboard for really low-level programers.</htmltext>
<tokenext>No , it needs a two button keyboard for really low-level programers .</tokentext>
<sentencetext>No, it needs a two button keyboard for really low-level programers.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162164</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258621320000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>move along nothing to see on this planet.</htmltext>
<tokenext>move along nothing to see on this planet .</tokentext>
<sentencetext>move along nothing to see on this planet.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161904</id>
	<title>This is not Computer Science</title>
	<author>Anonymous</author>
	<datestamp>1258663500000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>We'll see lots of joke replies here.  Computer Science is more concerned with O() notation--they have enough problems wrapping their heads around something like floating point numbers.</p></htmltext>
<tokenext>We 'll see lots of joke replies here .
Computer Science is more concerned with O ( ) notation--they have enough problems wrapping their heads around something like floating point numbers .</tokentext>
<sentencetext>We'll see lots of joke replies here.
Computer Science is more concerned with O() notation--they have enough problems wrapping their heads around something like floating point numbers.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168002</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258650960000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I understand the HHGTTG reference, but Planet of the Ape Descendants says......</p><p>Wait for it......</p><p>0xD000 (arguments)</p></htmltext>
<tokenext>I understand the HHGTTG reference , but Planet of the Ape Descendants says......Wait for it......0xD000 ( arguments )</tokentext>
<sentencetext>I understand the HHGTTG reference, but Planet of the Ape Descendants says......Wait for it......0xD000 (arguments)</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</id>
	<title>GOTO ...</title>
	<author>gstoddart</author>
	<datestamp>1258662180000</datestamp>
	<modclass>Funny</modclass>
	<modscore>4</modscore>
	<htmltext><p>I vote for GOTO as the only instruction.</p><p>That would be hilarious.</p><p>Cheers</p></htmltext>
<tokenext>I vote for GOTO as the only instruction.That would be hilarious.Cheers</tokentext>
<sentencetext>I vote for GOTO as the only instruction.That would be hilarious.Cheers</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161732</id>
	<title>AAA AA   A A</title>
	<author>Anonymous</author>
	<datestamp>1258663020000</datestamp>
	<modclass>Funny</modclass>
	<modscore>5</modscore>
	<htmltext><tt>AA A AA&nbsp; AAAA A&nbsp; AAA AA&nbsp; &nbsp;A A&nbsp; AA&nbsp; A A AAA&nbsp; &nbsp; A A AAAA&nbsp; &nbsp; AAA&nbsp; AAAA</tt></htmltext>
<tokenext>AA A AA   AAAA A   AAA AA     A A   AA   A A AAA     A A AAAA     AAA   AAAA</tokentext>
<sentencetext>AA A AA  AAAA A  AAA AA   A A  AA  A A AAA    A A AAAA    AAA  AAAA</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162874</id>
	<title>An old saying...</title>
	<author>Anonymous</author>
	<datestamp>1258623720000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>There's an old saying:</p><p>"Every program can be reduced by one instruction, and every program has at least one bug.<br>Therefore every programme can be reduced to one instruction, which is wrong."</p><p>Seems like we've just taken a big step towards proving that...</p></htmltext>
<tokenext>There 's an old saying : " Every program can be reduced by one instruction , and every program has at least one bug.Therefore every programme can be reduced to one instruction , which is wrong .
" Seems like we 've just taken a big step towards proving that.. .</tokentext>
<sentencetext>There's an old saying:"Every program can be reduced by one instruction, and every program has at least one bug.Therefore every programme can be reduced to one instruction, which is wrong.
"Seems like we've just taken a big step towards proving that...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162212</id>
	<title>I think it's misleading to call it 1 instruction</title>
	<author>shoor</author>
	<datestamp>1258621500000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext>There can be different architectures for computers, but, nowadays, for many of us, I'd say there is one particular model of an architecture that is likely to be the only one we're really familiar with, and that automatically comes to mind when one speaks of a computer architecture.  It's a rather compartmentalized architecture in which the CPU is the place where opcodes are executed and memory is just a big flat address space for data, including instructions.  This "transfer triggered" architecture strikes me as being not so much a 1 instruction computer as one where instructions are implemented in a less compartmentalized fashion, spread out among special units activated by addresses, as opposed to the more plain architecture where bit patterns on the address bus simply activate individual generic memory cells along with a read/write signal.  More than that may happen, cache memory comes into play with all it's complications for instance, but the 'model' for the programmer is that simple one.</htmltext>
<tokenext>There can be different architectures for computers , but , nowadays , for many of us , I 'd say there is one particular model of an architecture that is likely to be the only one we 're really familiar with , and that automatically comes to mind when one speaks of a computer architecture .
It 's a rather compartmentalized architecture in which the CPU is the place where opcodes are executed and memory is just a big flat address space for data , including instructions .
This " transfer triggered " architecture strikes me as being not so much a 1 instruction computer as one where instructions are implemented in a less compartmentalized fashion , spread out among special units activated by addresses , as opposed to the more plain architecture where bit patterns on the address bus simply activate individual generic memory cells along with a read/write signal .
More than that may happen , cache memory comes into play with all it 's complications for instance , but the 'model ' for the programmer is that simple one .</tokentext>
<sentencetext>There can be different architectures for computers, but, nowadays, for many of us, I'd say there is one particular model of an architecture that is likely to be the only one we're really familiar with, and that automatically comes to mind when one speaks of a computer architecture.
It's a rather compartmentalized architecture in which the CPU is the place where opcodes are executed and memory is just a big flat address space for data, including instructions.
This "transfer triggered" architecture strikes me as being not so much a 1 instruction computer as one where instructions are implemented in a less compartmentalized fashion, spread out among special units activated by addresses, as opposed to the more plain architecture where bit patterns on the address bus simply activate individual generic memory cells along with a read/write signal.
More than that may happen, cache memory comes into play with all it's complications for instance, but the 'model' for the programmer is that simple one.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163498</id>
	<title>Re:Not new, and not too useful</title>
	<author>Anonymous</author>
	<datestamp>1258625460000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>The monitor code in the article makes it look like it does have a macro assembler since it clearly uses lots of instructions. Why would you subroutine things like shifts and multiplies? Just make a new ALU destination so transfer 10 -&gt; ACC\_MULTIPLY or whatever.</p><p>From my experience he probably doesn't NEED the million gate FPGA but probably needs the memory on it or the routing resources. Same for speed. You could coax more speed out of this. It seems like it would be really easy to make new "instructions" by just plugging something into the bus.</p><p>Of course, I'd argue that the immediate move stuff is really a 2nd instruction. Picky picky.</p></htmltext>
<tokenext>The monitor code in the article makes it look like it does have a macro assembler since it clearly uses lots of instructions .
Why would you subroutine things like shifts and multiplies ?
Just make a new ALU destination so transfer 10 - &gt; ACC \ _MULTIPLY or whatever.From my experience he probably does n't NEED the million gate FPGA but probably needs the memory on it or the routing resources .
Same for speed .
You could coax more speed out of this .
It seems like it would be really easy to make new " instructions " by just plugging something into the bus.Of course , I 'd argue that the immediate move stuff is really a 2nd instruction .
Picky picky .</tokentext>
<sentencetext>The monitor code in the article makes it look like it does have a macro assembler since it clearly uses lots of instructions.
Why would you subroutine things like shifts and multiplies?
Just make a new ALU destination so transfer 10 -&gt; ACC\_MULTIPLY or whatever.From my experience he probably doesn't NEED the million gate FPGA but probably needs the memory on it or the routing resources.
Same for speed.
You could coax more speed out of this.
It seems like it would be really easy to make new "instructions" by just plugging something into the bus.Of course, I'd argue that the immediate move stuff is really a 2nd instruction.
Picky picky.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161782</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163484</id>
	<title>1998 called...</title>
	<author>Anonymous</author>
	<datestamp>1258625460000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I can't find his writeup anymore, but isn't this essentially Dave Taylor's 'pinky processor'?</p><p>http://tech.slashdot.org/article.pl?sid=98/06/06/136239</p></htmltext>
<tokenext>I ca n't find his writeup anymore , but is n't this essentially Dave Taylor 's 'pinky processor ' ? http : //tech.slashdot.org/article.pl ? sid = 98/06/06/136239</tokentext>
<sentencetext>I can't find his writeup anymore, but isn't this essentially Dave Taylor's 'pinky processor'?http://tech.slashdot.org/article.pl?sid=98/06/06/136239</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161756</id>
	<title>talking about...</title>
	<author>Ingcuervo</author>
	<datestamp>1258663080000</datestamp>
	<modclass>None</modclass>
	<modscore>-1</modscore>
	<htmltext>lazy coders..., I've known a lot of them, but this is ridiculus!</htmltext>
<tokenext>lazy coders... , I 've known a lot of them , but this is ridiculus !</tokentext>
<sentencetext>lazy coders..., I've known a lot of them, but this is ridiculus!</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163072</id>
	<title>One instruction 2000 addressing modes.</title>
	<author>tjstork</author>
	<datestamp>1258624320000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>wonder how many addressing modes there are...</p></htmltext>
<tokenext>wonder how many addressing modes there are.. .</tokentext>
<sentencetext>wonder how many addressing modes there are...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163636</id>
	<title>Patterson</title>
	<author>Anonymous</author>
	<datestamp>1258625880000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I remember reading on a Patterson book that the ultimate instruction was "Substract and Jump if zero". Everything could be implemented using that instruction alone.</p></htmltext>
<tokenext>I remember reading on a Patterson book that the ultimate instruction was " Substract and Jump if zero " .
Everything could be implemented using that instruction alone .</tokentext>
<sentencetext>I remember reading on a Patterson book that the ultimate instruction was "Substract and Jump if zero".
Everything could be implemented using that instruction alone.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164898</id>
	<title>... and one instruction ...</title>
	<author>Anonymous</author>
	<datestamp>1258629960000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>... to rule them all!</p></htmltext>
<tokenext>... to rule them all !</tokentext>
<sentencetext>... to rule them all!</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161846</id>
	<title>"One-der"</title>
	<author>porges</author>
	<datestamp>1258663320000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>4</modscore>
	<htmltext><p>The hyphen being so everyone doesn't call it "The O-need-er", as in <i>That Thing You Do</i>.</p></htmltext>
<tokenext>The hyphen being so everyone does n't call it " The O-need-er " , as in That Thing You Do .</tokentext>
<sentencetext>The hyphen being so everyone doesn't call it "The O-need-er", as in That Thing You Do.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30264674</id>
	<title>A Computer Architecture Book focusing on OISC</title>
	<author>Anonymous</author>
	<datestamp>1259497620000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Funny how things crop up when books have been written about the topic. There is a computer architecture book "Computer Architecture: A Minimalist Perspective" that examines computer architecture using the one instruction.</p><p>For those curious or interested the authors' website is http://www.caamp.info. As Mr. Spock says "Fascinating..." or perhaps "Pure energy" instead. It does take the intellectual exercise to a more in depth look. It seems OISC and RISC are the "minimalist philosophy" of computer architecture, that also pervades other areas of music, art, engineering--the "less is more" outlook. Whether its good or bad, order or chaos, franks or beans seems to remain a controversial topic for much heated debate.</p><p>Cheers, be well, and may your code compile...</p><p>Moses C. Kery</p></htmltext>
<tokenext>Funny how things crop up when books have been written about the topic .
There is a computer architecture book " Computer Architecture : A Minimalist Perspective " that examines computer architecture using the one instruction.For those curious or interested the authors ' website is http : //www.caamp.info .
As Mr. Spock says " Fascinating... " or perhaps " Pure energy " instead .
It does take the intellectual exercise to a more in depth look .
It seems OISC and RISC are the " minimalist philosophy " of computer architecture , that also pervades other areas of music , art , engineering--the " less is more " outlook .
Whether its good or bad , order or chaos , franks or beans seems to remain a controversial topic for much heated debate.Cheers , be well , and may your code compile...Moses C. Kery</tokentext>
<sentencetext>Funny how things crop up when books have been written about the topic.
There is a computer architecture book "Computer Architecture: A Minimalist Perspective" that examines computer architecture using the one instruction.For those curious or interested the authors' website is http://www.caamp.info.
As Mr. Spock says "Fascinating..." or perhaps "Pure energy" instead.
It does take the intellectual exercise to a more in depth look.
It seems OISC and RISC are the "minimalist philosophy" of computer architecture, that also pervades other areas of music, art, engineering--the "less is more" outlook.
Whether its good or bad, order or chaos, franks or beans seems to remain a controversial topic for much heated debate.Cheers, be well, and may your code compile...Moses C. Kery</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166136</id>
	<title>Re:"ideal for One-Der"?</title>
	<author>SharpFang</author>
	<datestamp>1258635240000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>FPGA is usually the prototype phase.</p><p>Actually, this could be implemented as a really small handful of transistors for the actual processor and a ton of various memory-mapped peripherials. Some of them being really simple old basic logic chips for ALU.</p><p>It would mean a simple version for cheap microcontrollers would be really cheap to make, a family of compatible devices of different scale would be possible, and extending/upgrading existing instruction set would be easy too.</p><p>The above is not a conflicting statement with the 1-instruction set idea. The MOV would not be really THE instruction set. The real instructions would be "place data in register A, read result from register B" and the memory map would be the real instruction set.</p><p>But I just can't see it for anything bigger. It might be used for massively multicore processors if the address and data bus could be shared somehow. But I think it would be the bottleneck really fast.</p></htmltext>
<tokenext>FPGA is usually the prototype phase.Actually , this could be implemented as a really small handful of transistors for the actual processor and a ton of various memory-mapped peripherials .
Some of them being really simple old basic logic chips for ALU.It would mean a simple version for cheap microcontrollers would be really cheap to make , a family of compatible devices of different scale would be possible , and extending/upgrading existing instruction set would be easy too.The above is not a conflicting statement with the 1-instruction set idea .
The MOV would not be really THE instruction set .
The real instructions would be " place data in register A , read result from register B " and the memory map would be the real instruction set.But I just ca n't see it for anything bigger .
It might be used for massively multicore processors if the address and data bus could be shared somehow .
But I think it would be the bottleneck really fast .</tokentext>
<sentencetext>FPGA is usually the prototype phase.Actually, this could be implemented as a really small handful of transistors for the actual processor and a ton of various memory-mapped peripherials.
Some of them being really simple old basic logic chips for ALU.It would mean a simple version for cheap microcontrollers would be really cheap to make, a family of compatible devices of different scale would be possible, and extending/upgrading existing instruction set would be easy too.The above is not a conflicting statement with the 1-instruction set idea.
The MOV would not be really THE instruction set.
The real instructions would be "place data in register A, read result from register B" and the memory map would be the real instruction set.But I just can't see it for anything bigger.
It might be used for massively multicore processors if the address and data bus could be shared somehow.
But I think it would be the bottleneck really fast.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162336</id>
	<title>Oneders?</title>
	<author>Anonymous</author>
	<datestamp>1258621860000</datestamp>
	<modclass>Funny</modclass>
	<modscore>1</modscore>
	<htmltext><p>AH the ONEDERS! - didn't that band have to change their name to the wonders? silly movies.... GO ONEDERS! pronounced (oh-knee-ders)</p></htmltext>
<tokenext>AH the ONEDERS !
- did n't that band have to change their name to the wonders ?
silly movies.... GO ONEDERS !
pronounced ( oh-knee-ders )</tokentext>
<sentencetext>AH the ONEDERS!
- didn't that band have to change their name to the wonders?
silly movies.... GO ONEDERS!
pronounced (oh-knee-ders)</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161598</id>
	<title>Re:GOTO ...</title>
	<author>jeffmeden</author>
	<datestamp>1258662600000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I think I was in a high school 'comp sci for dummies' class based on that principle.  You would be surprised how much qBasic can do with generous use of GOTO.</p><p>Well, at least, it seemed like an impressive program at the time.  Good thing I don't write code for a living!</p></htmltext>
<tokenext>I think I was in a high school 'comp sci for dummies ' class based on that principle .
You would be surprised how much qBasic can do with generous use of GOTO.Well , at least , it seemed like an impressive program at the time .
Good thing I do n't write code for a living !</tokentext>
<sentencetext>I think I was in a high school 'comp sci for dummies' class based on that principle.
You would be surprised how much qBasic can do with generous use of GOTO.Well, at least, it seemed like an impressive program at the time.
Good thing I don't write code for a living!</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162322</id>
	<title>Actually the real point</title>
	<author>Anonymous</author>
	<datestamp>1258621800000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>If you read all the way through he talks about how the bus-like architecture would let you reconfigure the CPU although he doesn't have any tools for that. So you could scan your program, decide on an optimal architecture for it (I need 4 accumulators, 2 stacks, and 4 floating point units) and then compile a program just for that "new" CPU. You could do that with other schemes, I guess, but it becomes hard becuase the data path is usually pretty much wired one way. This is just a bus.</p><p>Also, it looks like it would be nothing to add new "instructions" just by plugging relatively simple boxes onto the bus.</p><p>There are a couple of old CPUs that did this (Burroughs maybe? I forget).</p></htmltext>
<tokenext>If you read all the way through he talks about how the bus-like architecture would let you reconfigure the CPU although he does n't have any tools for that .
So you could scan your program , decide on an optimal architecture for it ( I need 4 accumulators , 2 stacks , and 4 floating point units ) and then compile a program just for that " new " CPU .
You could do that with other schemes , I guess , but it becomes hard becuase the data path is usually pretty much wired one way .
This is just a bus.Also , it looks like it would be nothing to add new " instructions " just by plugging relatively simple boxes onto the bus.There are a couple of old CPUs that did this ( Burroughs maybe ?
I forget ) .</tokentext>
<sentencetext>If you read all the way through he talks about how the bus-like architecture would let you reconfigure the CPU although he doesn't have any tools for that.
So you could scan your program, decide on an optimal architecture for it (I need 4 accumulators, 2 stacks, and 4 floating point units) and then compile a program just for that "new" CPU.
You could do that with other schemes, I guess, but it becomes hard becuase the data path is usually pretty much wired one way.
This is just a bus.Also, it looks like it would be nothing to add new "instructions" just by plugging relatively simple boxes onto the bus.There are a couple of old CPUs that did this (Burroughs maybe?
I forget).</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168544</id>
	<title>Re:"ideal for One-Der"?</title>
	<author>Anonymous</author>
	<datestamp>1258656720000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Let's generalize it, then. TTA is the single instruction, and NAND is the single physical gate. All else can be thus expressed (if a bit verbosely).</p><p>Now all we need is that NAND chip to run at forty-trillion giga-shizzles, and we'll be on a par with today's consumer-grade hardware.</p></htmltext>
<tokenext>Let 's generalize it , then .
TTA is the single instruction , and NAND is the single physical gate .
All else can be thus expressed ( if a bit verbosely ) .Now all we need is that NAND chip to run at forty-trillion giga-shizzles , and we 'll be on a par with today 's consumer-grade hardware .</tokentext>
<sentencetext>Let's generalize it, then.
TTA is the single instruction, and NAND is the single physical gate.
All else can be thus expressed (if a bit verbosely).Now all we need is that NAND chip to run at forty-trillion giga-shizzles, and we'll be on a par with today's consumer-grade hardware.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161946</id>
	<title>Used to work for someone doing this</title>
	<author>JKR</author>
	<datestamp>1258663680000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The idea of offloading software functions onto custom hardware built around a TTA is interesting - 5 years ago I used to work for <a href="http://www.criticalblue.com/" title="criticalblue.com">Critical Blue</a> [criticalblue.com] who were writing software to design and build those custom processors and optimise an ISA for them. Worth a look.</htmltext>
<tokenext>The idea of offloading software functions onto custom hardware built around a TTA is interesting - 5 years ago I used to work for Critical Blue [ criticalblue.com ] who were writing software to design and build those custom processors and optimise an ISA for them .
Worth a look .</tokentext>
<sentencetext>The idea of offloading software functions onto custom hardware built around a TTA is interesting - 5 years ago I used to work for Critical Blue [criticalblue.com] who were writing software to design and build those custom processors and optimise an ISA for them.
Worth a look.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162892</id>
	<title>Re:Can be a bit tricky to program...</title>
	<author>multipart/mixed</author>
	<datestamp>1258623780000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>Interesting.</p><p>First off, your one-instruction CPU, I guess you didn't need to express the instruction in machine code, just the arguments.</p><p>Here's the funny question, why not develop an assembler with synthetic instructions, like SPARC v9?  It would certainly make it easier to program.</p></htmltext>
<tokenext>Interesting.First off , your one-instruction CPU , I guess you did n't need to express the instruction in machine code , just the arguments.Here 's the funny question , why not develop an assembler with synthetic instructions , like SPARC v9 ?
It would certainly make it easier to program .</tokentext>
<sentencetext>Interesting.First off, your one-instruction CPU, I guess you didn't need to express the instruction in machine code, just the arguments.Here's the funny question, why not develop an assembler with synthetic instructions, like SPARC v9?
It would certainly make it easier to program.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161468</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163340</id>
	<title>Re:Not new, and not too useful</title>
	<author>Bender\_</author>
	<datestamp>1258625040000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Fewer instructions does not always mean that the CPU architecture gets more optimized.</p><p>To my knowledge, in terms of gatecount this is the most efficient CPU around:</p><p><a href="http://www.opencores.org/project,mcpu" title="opencores.org">http://www.opencores.org/project,mcpu</a> [opencores.org]</p><p>32 Macrocells in a CPLD.</p></htmltext>
<tokenext>Fewer instructions does not always mean that the CPU architecture gets more optimized.To my knowledge , in terms of gatecount this is the most efficient CPU around : http : //www.opencores.org/project,mcpu [ opencores.org ] 32 Macrocells in a CPLD .</tokentext>
<sentencetext>Fewer instructions does not always mean that the CPU architecture gets more optimized.To my knowledge, in terms of gatecount this is the most efficient CPU around:http://www.opencores.org/project,mcpu [opencores.org]32 Macrocells in a CPLD.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161782</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161446</id>
	<title>And for Slashdot users, that one instruction is...</title>
	<author>Anonymous</author>
	<datestamp>1258662120000</datestamp>
	<modclass>Troll</modclass>
	<modscore>-1</modscore>
	<htmltext><p><b>Troll</b></p></htmltext>
<tokenext>Troll</tokentext>
<sentencetext>Troll</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161354</id>
	<title>But can it</title>
	<author>Anonymous</author>
	<datestamp>1258661880000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>But can it run Vista?</htmltext>
<tokenext>But can it run Vista ?</tokentext>
<sentencetext>But can it run Vista?</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163364</id>
	<title>Great, but...</title>
	<author>CompressedAir</author>
	<datestamp>1258625100000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>... is it pronounced "O-knee-der" or "O-ned-der"?</p><p>You know, every time it does that thing it does.</p></htmltext>
<tokenext>... is it pronounced " O-knee-der " or " O-ned-der " ? You know , every time it does that thing it does .</tokentext>
<sentencetext>... is it pronounced "O-knee-der" or "O-ned-der"?You know, every time it does that thing it does.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168506</id>
	<title>Re:One instruction 2000 addressing modes.</title>
	<author>wd5gnr</author>
	<datestamp>1258656420000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The machine directly addresses registers and functional units. The register bank had an indirect register much like a PIC's FSR register scheme. All memory access is via functional units. So you can design what memory addressing modes you want. The default machine has two memory access blocks. One has two pointers that can pre or post incremented by a constant (or not) and indexed. The other block implements a stack and can access off fixed offsets of the stack as well.

But the memory FUs could be arbitrarily complex implementing an MMU, segmented memory, block transfers, and any addressing mode you might require. If you did, for example, an MMU and kept the same interface as the memory FU (perhaps adding a second FU to control the page tables) the change would be transparent to application code.</htmltext>
<tokenext>The machine directly addresses registers and functional units .
The register bank had an indirect register much like a PIC 's FSR register scheme .
All memory access is via functional units .
So you can design what memory addressing modes you want .
The default machine has two memory access blocks .
One has two pointers that can pre or post incremented by a constant ( or not ) and indexed .
The other block implements a stack and can access off fixed offsets of the stack as well .
But the memory FUs could be arbitrarily complex implementing an MMU , segmented memory , block transfers , and any addressing mode you might require .
If you did , for example , an MMU and kept the same interface as the memory FU ( perhaps adding a second FU to control the page tables ) the change would be transparent to application code .</tokentext>
<sentencetext>The machine directly addresses registers and functional units.
The register bank had an indirect register much like a PIC's FSR register scheme.
All memory access is via functional units.
So you can design what memory addressing modes you want.
The default machine has two memory access blocks.
One has two pointers that can pre or post incremented by a constant (or not) and indexed.
The other block implements a stack and can access off fixed offsets of the stack as well.
But the memory FUs could be arbitrarily complex implementing an MMU, segmented memory, block transfers, and any addressing mode you might require.
If you did, for example, an MMU and kept the same interface as the memory FU (perhaps adding a second FU to control the page tables) the change would be transparent to application code.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163072</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161862</id>
	<title>Far better embedded CPUs...</title>
	<author>Anonymous</author>
	<datestamp>1258663440000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>All the FPGA vendors have their own embedded CPU cores, such as the <a href="http://en.wikipedia.org/wiki/MicroBlaze" title="wikipedia.org">Xilinx Microblaze</a> [wikipedia.org] and the <a href="http://en.wikipedia.org/wiki/Nios\_II" title="wikipedia.org">Altera NIOS II</a> [wikipedia.org] which are very small FPGA-embeddable CPU cores.</p><p>You also have free options that aren't tied to specific FPGAs like the <a href="http://en.wikipedia.org/wiki/LEON#LEON3" title="wikipedia.org">LEON sparc-compatible processors</a> [wikipedia.org].</p></htmltext>
<tokenext>All the FPGA vendors have their own embedded CPU cores , such as the Xilinx Microblaze [ wikipedia.org ] and the Altera NIOS II [ wikipedia.org ] which are very small FPGA-embeddable CPU cores.You also have free options that are n't tied to specific FPGAs like the LEON sparc-compatible processors [ wikipedia.org ] .</tokentext>
<sentencetext>All the FPGA vendors have their own embedded CPU cores, such as the Xilinx Microblaze [wikipedia.org] and the Altera NIOS II [wikipedia.org] which are very small FPGA-embeddable CPU cores.You also have free options that aren't tied to specific FPGAs like the LEON sparc-compatible processors [wikipedia.org].</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163158</id>
	<title>I prefer HALT</title>
	<author>syousef</author>
	<datestamp>1258624560000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>The only valid program is a single HALT instruction.</p></htmltext>
<tokenext>The only valid program is a single HALT instruction .</tokentext>
<sentencetext>The only valid program is a single HALT instruction.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161726</id>
	<title>Memory of this from Engineering School</title>
	<author>systemeng</author>
	<datestamp>1258662960000</datestamp>
	<modclass>Funny</modclass>
	<modscore>3</modscore>
	<htmltext>I remember hearing about building a one instruction computer back in engineering school.  The one I heard about was based on Subtract and Branch if Not Equal.  My roommate at the time figured it ought to be a way to get a very high clock rate.  It seems like he found a proof in a hoary old book that such a computer was in fact Turing complete.  I'm sure I'll get flamed for posting a vague recollection but. . . here it is.</htmltext>
<tokenext>I remember hearing about building a one instruction computer back in engineering school .
The one I heard about was based on Subtract and Branch if Not Equal .
My roommate at the time figured it ought to be a way to get a very high clock rate .
It seems like he found a proof in a hoary old book that such a computer was in fact Turing complete .
I 'm sure I 'll get flamed for posting a vague recollection but .
. .
here it is .</tokentext>
<sentencetext>I remember hearing about building a one instruction computer back in engineering school.
The one I heard about was based on Subtract and Branch if Not Equal.
My roommate at the time figured it ought to be a way to get a very high clock rate.
It seems like he found a proof in a hoary old book that such a computer was in fact Turing complete.
I'm sure I'll get flamed for posting a vague recollection but.
. .
here it is.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30167566</id>
	<title>This is what the ASM code looks like...</title>
	<author>marciot</author>
	<datestamp>1258646040000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><nobr> <wbr></nobr>.MODEL Small<nobr> <wbr></nobr>.STACK 100h<nobr> <wbr></nobr>.DATA<br>
&nbsp; &nbsp; &nbsp; msg db 'Hello, world!$'<nobr> <wbr></nobr>.CODE<br>
&nbsp; &nbsp; start:<br>
&nbsp; &nbsp; simon\_says mov ah, 09h<br>
&nbsp; &nbsp; simon\_says lea dx, msg<br>
&nbsp; &nbsp; simon\_says int 21h<br>
&nbsp; &nbsp; simon\_says mov ax,4C00h<br>
&nbsp; &nbsp; simon\_says int 21h<br>
&nbsp; &nbsp; end start</p><p>(source: wikipedia)</p></htmltext>
<tokenext>.MODEL Small .STACK 100h .DATA       msg db 'Hello , world ! $ ' .CODE     start :     simon \ _says mov ah , 09h     simon \ _says lea dx , msg     simon \ _says int 21h     simon \ _says mov ax,4C00h     simon \ _says int 21h     end start ( source : wikipedia )</tokentext>
<sentencetext> .MODEL Small .STACK 100h .DATA
      msg db 'Hello, world!$' .CODE
    start:
    simon\_says mov ah, 09h
    simon\_says lea dx, msg
    simon\_says int 21h
    simon\_says mov ax,4C00h
    simon\_says int 21h
    end start(source: wikipedia)</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166162</id>
	<title>Re:"ideal for One-Der"?</title>
	<author>suburbanmediocrity</author>
	<datestamp>1258635360000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Sounds like IBM's Daisy.<p>

 <a href="http://www.research.ibm.com/daisy/" title="ibm.com" rel="nofollow">http://www.research.ibm.com/daisy/</a> [ibm.com]</p></htmltext>
<tokenext>Sounds like IBM 's Daisy .
http : //www.research.ibm.com/daisy/ [ ibm.com ]</tokentext>
<sentencetext>Sounds like IBM's Daisy.
http://www.research.ibm.com/daisy/ [ibm.com]</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162672</id>
	<title>Perfect for running CPM/86...</title>
	<author>Anonymous</author>
	<datestamp>1258622940000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>... the OS only had one instruction - "PIP" ("Peripheral Interchange Program").</p></htmltext>
<tokenext>... the OS only had one instruction - " PIP " ( " Peripheral Interchange Program " ) .</tokentext>
<sentencetext>... the OS only had one instruction - "PIP" ("Peripheral Interchange Program").</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164686</id>
	<title>This isn't a new idea</title>
	<author>Theovon</author>
	<datestamp>1258629060000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Of course, that's true about just about everything.  Back in the 80's, I heard of this being referred to as a MISC processor (minimal instruction set computer).</p><p>Of course, it's cool that this guy actually BUILT one.<nobr> <wbr></nobr>:)</p></htmltext>
<tokenext>Of course , that 's true about just about everything .
Back in the 80 's , I heard of this being referred to as a MISC processor ( minimal instruction set computer ) .Of course , it 's cool that this guy actually BUILT one .
: )</tokentext>
<sentencetext>Of course, that's true about just about everything.
Back in the 80's, I heard of this being referred to as a MISC processor (minimal instruction set computer).Of course, it's cool that this guy actually BUILT one.
:)</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30194186</id>
	<title>Re:Not new, and not too useful</title>
	<author>renoX</author>
	<datestamp>1258911540000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>&gt;It's a lose on performance. It's a lose on code density.</p><p>More importantly it's a loss of ISA compatibility, as x86 has shown what backward compatibility is important..</p></htmltext>
<tokenext>&gt; It 's a lose on performance .
It 's a lose on code density.More importantly it 's a loss of ISA compatibility , as x86 has shown what backward compatibility is important. .</tokentext>
<sentencetext>&gt;It's a lose on performance.
It's a lose on code density.More importantly it's a loss of ISA compatibility, as x86 has shown what backward compatibility is important..</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161782</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161388</id>
	<title>nihilist</title>
	<author>Anonymous</author>
	<datestamp>1258662000000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>4</modscore>
	<htmltext><p>vaguely reminds me of the nihilist language joke. A language that realizes that ultimately all things are futile and irrelevant, thus allowing all instructions to be reduced to a no-op.</p></htmltext>
<tokenext>vaguely reminds me of the nihilist language joke .
A language that realizes that ultimately all things are futile and irrelevant , thus allowing all instructions to be reduced to a no-op .</tokentext>
<sentencetext>vaguely reminds me of the nihilist language joke.
A language that realizes that ultimately all things are futile and irrelevant, thus allowing all instructions to be reduced to a no-op.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161790</id>
	<title>RISC vs CISC - sigh</title>
	<author>Anonymous</author>
	<datestamp>1258663140000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext>"The advantages of RISC are well known &mdash; simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution."

I know this has been argued to death already - but it just isn't completely true that a RISC has advantages over a CISC.  The gain in speed is usually negated by the lack of expressiveness and the number of registers would help a CISC just as much as a RISC.  Why is this being dragged up again?</htmltext>
<tokenext>" The advantages of RISC are well known    simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds , more registers , and pipelining to provide the appearance of single-cycle execution .
" I know this has been argued to death already - but it just is n't completely true that a RISC has advantages over a CISC .
The gain in speed is usually negated by the lack of expressiveness and the number of registers would help a CISC just as much as a RISC .
Why is this being dragged up again ?</tokentext>
<sentencetext>"The advantages of RISC are well known — simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution.
"

I know this has been argued to death already - but it just isn't completely true that a RISC has advantages over a CISC.
The gain in speed is usually negated by the lack of expressiveness and the number of registers would help a CISC just as much as a RISC.
Why is this being dragged up again?</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161828</id>
	<title>if the instruction is NAND</title>
	<author>bugs2squash</author>
	<datestamp>1258663260000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I think you can get it to compute anything - if you have enough of them.</htmltext>
<tokenext>I think you can get it to compute anything - if you have enough of them .</tokentext>
<sentencetext>I think you can get it to compute anything - if you have enough of them.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162716</id>
	<title>I've seen this before.</title>
	<author>Anonymous</author>
	<datestamp>1258623120000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>It seems to me like all they're trying to do is reduce risc.</p></htmltext>
<tokenext>It seems to me like all they 're trying to do is reduce risc .</tokentext>
<sentencetext>It seems to me like all they're trying to do is reduce risc.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164284</id>
	<title>Could really crank up the speeds</title>
	<author>straponego</author>
	<datestamp>1258627740000</datestamp>
	<modclass>Funny</modclass>
	<modscore>3</modscore>
	<htmltext>...if the one instruction is NOP.   He could easily crack the petanop barrier.</htmltext>
<tokenext>...if the one instruction is NOP .
He could easily crack the petanop barrier .</tokentext>
<sentencetext>...if the one instruction is NOP.
He could easily crack the petanop barrier.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163718</id>
	<title>Re:Not the Ultimate RISC Architecture</title>
	<author>maxwell demon</author>
	<datestamp>1258626180000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I vote for systems with a negative number of instructions!<nobr> <wbr></nobr>:-)<br>You just tell the computer what <em>not</em> to do, and the computer does something which you didn't forbid.</p></htmltext>
<tokenext>I vote for systems with a negative number of instructions !
: - ) You just tell the computer what not to do , and the computer does something which you did n't forbid .</tokentext>
<sentencetext>I vote for systems with a negative number of instructions!
:-)You just tell the computer what not to do, and the computer does something which you didn't forbid.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161714</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162174</id>
	<title>Re:Ummmm</title>
	<author>Anonymous</author>
	<datestamp>1258621320000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>5</modscore>
	<htmltext><p><i>Is it just me, or does this sound like RISC fanboyism from the 1990s? The "advantages" of RISC are not nearly so clear these days. Indeed, it is getting rather hard to find real RISC chips. While there are chips based on RISC ISA idea (like being load/store and such), they are not RISC. RISC is about having few instructions and instructions that are simple and only do one thing. Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.</i></p><p>I wouldn't say that's what RISC was about at all; the basic idea was to have only instructions that could be implemented using a few simple pipeline stages.  This is a substantial improvement over the microcoded architectures that were prevalent prior to RISC, because it can be much more easily pipelined (or, indeed, pipelined at all).  I don't see SIMD as incompatible with RISC in any fashion; it just happens that the instruction operates on very wide data, but it's still a relatively simple instruction that should be able to complete quite quickly.</p><p><i>These days complex processors are the norm. They have special instructions for special things and that seems to work well. RISC is just not very common, even in systems with a RISC heritage.</i></p><p>I'd say it's more the other way around.  Even in systems with a CISC ISA (e.g. x86), you tend to find that under the hood the CISC instructions are translated into a series of microops that are then dispatched in a system that is somewhat RISC-like.  The most common processor family in the world is the ARM family, and all of those processors subscribe pretty well to the original principles of RISC, from instruction set to internal design of the processor core.</p><p>All of these are much more faithful to the principles of RISC than the chip described in TFA, whose instruction performs two memory accesses on each execution -- note that the removal of such instructions and consequent simplification of the execution pipeline (by having only a single pipleline stage that could access memory) was the original motivation behind RISC architectures.</p></htmltext>
<tokenext>Is it just me , or does this sound like RISC fanboyism from the 1990s ?
The " advantages " of RISC are not nearly so clear these days .
Indeed , it is getting rather hard to find real RISC chips .
While there are chips based on RISC ISA idea ( like being load/store and such ) , they are not RISC .
RISC is about having few instructions and instructions that are simple and only do one thing .
Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.I would n't say that 's what RISC was about at all ; the basic idea was to have only instructions that could be implemented using a few simple pipeline stages .
This is a substantial improvement over the microcoded architectures that were prevalent prior to RISC , because it can be much more easily pipelined ( or , indeed , pipelined at all ) .
I do n't see SIMD as incompatible with RISC in any fashion ; it just happens that the instruction operates on very wide data , but it 's still a relatively simple instruction that should be able to complete quite quickly.These days complex processors are the norm .
They have special instructions for special things and that seems to work well .
RISC is just not very common , even in systems with a RISC heritage.I 'd say it 's more the other way around .
Even in systems with a CISC ISA ( e.g .
x86 ) , you tend to find that under the hood the CISC instructions are translated into a series of microops that are then dispatched in a system that is somewhat RISC-like .
The most common processor family in the world is the ARM family , and all of those processors subscribe pretty well to the original principles of RISC , from instruction set to internal design of the processor core.All of these are much more faithful to the principles of RISC than the chip described in TFA , whose instruction performs two memory accesses on each execution -- note that the removal of such instructions and consequent simplification of the execution pipeline ( by having only a single pipleline stage that could access memory ) was the original motivation behind RISC architectures .</tokentext>
<sentencetext>Is it just me, or does this sound like RISC fanboyism from the 1990s?
The "advantages" of RISC are not nearly so clear these days.
Indeed, it is getting rather hard to find real RISC chips.
While there are chips based on RISC ISA idea (like being load/store and such), they are not RISC.
RISC is about having few instructions and instructions that are simple and only do one thing.
Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.I wouldn't say that's what RISC was about at all; the basic idea was to have only instructions that could be implemented using a few simple pipeline stages.
This is a substantial improvement over the microcoded architectures that were prevalent prior to RISC, because it can be much more easily pipelined (or, indeed, pipelined at all).
I don't see SIMD as incompatible with RISC in any fashion; it just happens that the instruction operates on very wide data, but it's still a relatively simple instruction that should be able to complete quite quickly.These days complex processors are the norm.
They have special instructions for special things and that seems to work well.
RISC is just not very common, even in systems with a RISC heritage.I'd say it's more the other way around.
Even in systems with a CISC ISA (e.g.
x86), you tend to find that under the hood the CISC instructions are translated into a series of microops that are then dispatched in a system that is somewhat RISC-like.
The most common processor family in the world is the ARM family, and all of those processors subscribe pretty well to the original principles of RISC, from instruction set to internal design of the processor core.All of these are much more faithful to the principles of RISC than the chip described in TFA, whose instruction performs two memory accesses on each execution -- note that the removal of such instructions and consequent simplification of the execution pipeline (by having only a single pipleline stage that could access memory) was the original motivation behind RISC architectures.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161744</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162384</id>
	<title>Isn't it cheating?</title>
	<author>HexaByte</author>
	<datestamp>1258622040000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Isn't it cheating to have a CPU with one instruction that relies on custom hardware to do the rest of the instructions?  You're just re-defining the CPU and adding more hardware to 'simplify' the CPU!</htmltext>
<tokenext>Is n't it cheating to have a CPU with one instruction that relies on custom hardware to do the rest of the instructions ?
You 're just re-defining the CPU and adding more hardware to 'simplify ' the CPU !</tokentext>
<sentencetext>Isn't it cheating to have a CPU with one instruction that relies on custom hardware to do the rest of the instructions?
You're just re-defining the CPU and adding more hardware to 'simplify' the CPU!</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</id>
	<title>That instruction is ..........</title>
	<author>140Mandak262Jamuna</author>
	<datestamp>1258661760000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>4</modscore>
	<htmltext>-------------drum roll <p>

0x2A</p><p>

That is the ultimate instruction.</p></htmltext>
<tokenext>-------------drum roll 0x2A That is the ultimate instruction .</tokentext>
<sentencetext>-------------drum roll 

0x2A

That is the ultimate instruction.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161652</id>
	<title>One instruction...</title>
	<author>Anonymous</author>
	<datestamp>1258662780000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>3</modscore>
	<htmltext><p>... whose first operand is the task to perform.  Followed by the necessary operands for that task.</p></htmltext>
<tokenext>... whose first operand is the task to perform .
Followed by the necessary operands for that task .</tokentext>
<sentencetext>... whose first operand is the task to perform.
Followed by the necessary operands for that task.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161938</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258663680000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Fail! That's not even a 32-bit instruction. Everyone knows the ultimate instruction is <tt>0xDEADBEEF</tt>!</p></htmltext>
<tokenext>Fail !
That 's not even a 32-bit instruction .
Everyone knows the ultimate instruction is 0xDEADBEEF !</tokentext>
<sentencetext>Fail!
That's not even a 32-bit instruction.
Everyone knows the ultimate instruction is 0xDEADBEEF!</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161498</id>
	<title>Re:That instruction is ..........</title>
	<author>Megane</author>
	<datestamp>1258662300000</datestamp>
	<modclass>Redundant</modclass>
	<modscore>0</modscore>
	<htmltext>f0 0f c7 c8</htmltext>
<tokenext>f0 0f c7 c8</tokentext>
<sentencetext>f0 0f c7 c8</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163886</id>
	<title>One-Der...</title>
	<author>Anonymous</author>
	<datestamp>1258626660000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I once did microcoding on an Array Processor back almost 30 years ago which worked with the UNIVAC 1100/80 mainframe... it was implemented by DataWest.</p><p>Using the 1100 Meta-Assembler we wrote 288bit long instructions that handled moves through the various bits of the machine with 72bit per slice (there were 4 slices).</p><p>And, yeah, the clock rate the 100ns/cycle so there was an instruction fetch 10 times a microsecond.  This limit was do to being built using TTL...</p><p>And to think that this machine had a theoretical peak throughput of 120MFlops...  and, I recall, could sustain 80 MFlops.</p><p>So, yeah, this could happen.</p></htmltext>
<tokenext>I once did microcoding on an Array Processor back almost 30 years ago which worked with the UNIVAC 1100/80 mainframe... it was implemented by DataWest.Using the 1100 Meta-Assembler we wrote 288bit long instructions that handled moves through the various bits of the machine with 72bit per slice ( there were 4 slices ) .And , yeah , the clock rate the 100ns/cycle so there was an instruction fetch 10 times a microsecond .
This limit was do to being built using TTL...And to think that this machine had a theoretical peak throughput of 120MFlops... and , I recall , could sustain 80 MFlops.So , yeah , this could happen .</tokentext>
<sentencetext>I once did microcoding on an Array Processor back almost 30 years ago which worked with the UNIVAC 1100/80 mainframe... it was implemented by DataWest.Using the 1100 Meta-Assembler we wrote 288bit long instructions that handled moves through the various bits of the machine with 72bit per slice (there were 4 slices).And, yeah, the clock rate the 100ns/cycle so there was an instruction fetch 10 times a microsecond.
This limit was do to being built using TTL...And to think that this machine had a theoretical peak throughput of 120MFlops...  and, I recall, could sustain 80 MFlops.So, yeah, this could happen.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162644</id>
	<title>...to rule them all!</title>
	<author>Anonymous</author>
	<datestamp>1258622820000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>But, err, there are no instructions for it to rule. Oh well.</htmltext>
<tokenext>But , err , there are no instructions for it to rule .
Oh well .</tokentext>
<sentencetext>But, err, there are no instructions for it to rule.
Oh well.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161652</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162630</id>
	<title>Re:That instruction is ..........</title>
	<author>hitnrunrambler</author>
	<datestamp>1258622820000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Apparently Douglas Adams was wrong.... on slashdot people DO make jokes in base 13.</p></htmltext>
<tokenext>Apparently Douglas Adams was wrong.... on slashdot people DO make jokes in base 13 .</tokentext>
<sentencetext>Apparently Douglas Adams was wrong.... on slashdot people DO make jokes in base 13.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161728</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161752</id>
	<title>All on one page version</title>
	<author>KnownIssues</author>
	<datestamp>1258663080000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><a href="http://www.ddj.com/article/printableArticle.jhtml;jsessionid=BRDFOGSH1MDJFQE1GHRSKH4ATMY32JVN?articleID=221800122&amp;dept\_url=/embedded/" title="ddj.com" rel="nofollow">Link to the Print version</a> [ddj.com]--article on one page with no advertising since I haven't seen that posted yet.</htmltext>
<tokenext>Link to the Print version [ ddj.com ] --article on one page with no advertising since I have n't seen that posted yet .</tokentext>
<sentencetext>Link to the Print version [ddj.com]--article on one page with no advertising since I haven't seen that posted yet.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163780</id>
	<title>Re:GOTO ...</title>
	<author>Anonymous</author>
	<datestamp>1258626360000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>0x20090d0a would be even better - especially for secure code</p></htmltext>
<tokenext>0x20090d0a would be even better - especially for secure code</tokentext>
<sentencetext>0x20090d0a would be even better - especially for secure code</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164400</id>
	<title>Re:What's the one instruction?</title>
	<author>beh</author>
	<datestamp>1258628160000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>No, It's been proven that 'do-what-I-want' leads to misunderstandings and bugs...</p><p>It's DWIM (Do-What-I-MEAN!) you're after...</p></htmltext>
<tokenext>No , It 's been proven that 'do-what-I-want ' leads to misunderstandings and bugs...It 's DWIM ( Do-What-I-MEAN !
) you 're after.. .</tokentext>
<sentencetext>No, It's been proven that 'do-what-I-want' leads to misunderstandings and bugs...It's DWIM (Do-What-I-MEAN!
) you're after...</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161626</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30190884</id>
	<title>One-Der on YouTube</title>
	<author>wd5gnr</author>
	<datestamp>1258823700000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><a href="http://www.youtube.com/watch?v=YYdpRV29\_Y8" title="youtube.com" rel="nofollow">http://www.youtube.com/watch?v=YYdpRV29\_Y8</a> [youtube.com] - Actual 2nd gen hardware<br>

<a href="http://www.youtube.com/watch?v=KnQGcoe6oGg" title="youtube.com" rel="nofollow">http://www.youtube.com/watch?v=KnQGcoe6oGg</a> [youtube.com] - Software simulator</htmltext>
<tokenext>http : //www.youtube.com/watch ? v = YYdpRV29 \ _Y8 [ youtube.com ] - Actual 2nd gen hardware http : //www.youtube.com/watch ? v = KnQGcoe6oGg [ youtube.com ] - Software simulator</tokentext>
<sentencetext>http://www.youtube.com/watch?v=YYdpRV29\_Y8 [youtube.com] - Actual 2nd gen hardware

http://www.youtube.com/watch?v=KnQGcoe6oGg [youtube.com] - Software simulator</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161942</id>
	<title>Re:Can be a bit tricky to program...</title>
	<author>Anonymous</author>
	<datestamp>1258663680000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>4</modscore>
	<htmltext>For a few seconds there, I thought you said grade school. Made me feel very inferior<nobr> <wbr></nobr>:) Wouldn't the complexities of programming it be handled by a compiler? If someone managed to write one for a 1 instruction processor?</htmltext>
<tokenext>For a few seconds there , I thought you said grade school .
Made me feel very inferior : ) Would n't the complexities of programming it be handled by a compiler ?
If someone managed to write one for a 1 instruction processor ?</tokentext>
<sentencetext>For a few seconds there, I thought you said grade school.
Made me feel very inferior :) Wouldn't the complexities of programming it be handled by a compiler?
If someone managed to write one for a 1 instruction processor?</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161468</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162342</id>
	<title>It's not working</title>
	<author>Anonymous</author>
	<datestamp>1258621860000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The point was supposed to be speed.  So, he gets 10 MHz?  That's not very impressive...</htmltext>
<tokenext>The point was supposed to be speed .
So , he gets 10 MHz ?
That 's not very impressive.. .</tokentext>
<sentencetext>The point was supposed to be speed.
So, he gets 10 MHz?
That's not very impressive...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168564</id>
	<title>One instruction OS</title>
	<author>Anonymous</author>
	<datestamp>1258656960000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>That would be great for running Windows; all you need is one instruction:</p><p>HLT.</p></htmltext>
<tokenext>That would be great for running Windows ; all you need is one instruction : HLT .</tokentext>
<sentencetext>That would be great for running Windows; all you need is one instruction:HLT.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162142</id>
	<title>Re:GOTO ...</title>
	<author>Quiet\_Desperation</author>
	<datestamp>1258664340000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>NOOP would be funnier.</htmltext>
<tokenext>NOOP would be funnier .</tokentext>
<sentencetext>NOOP would be funnier.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162366</id>
	<title>Re:GOTO ...</title>
	<author>ctrl-alt-canc</author>
	<datestamp>1258621980000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>A NOP is better. Further developments will make available an indexed NOP, so that the CPU will jump and do nothing at the same time.</htmltext>
<tokenext>A NOP is better .
Further developments will make available an indexed NOP , so that the CPU will jump and do nothing at the same time .</tokentext>
<sentencetext>A NOP is better.
Further developments will make available an indexed NOP, so that the CPU will jump and do nothing at the same time.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164028</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258627020000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>0x2A=0. Now was that so hard?</p></htmltext>
<tokenext>0x2A = 0 .
Now was that so hard ?</tokentext>
<sentencetext>0x2A=0.
Now was that so hard?</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30167732</id>
	<title>Pardon me for injecting something serious, but...</title>
	<author>Bruce Perens</author>
	<datestamp>1258648140000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext>It seems to me that a transfer oriented architecture is conceptually very easy to parallelize.</htmltext>
<tokenext>It seems to me that a transfer oriented architecture is conceptually very easy to parallelize .</tokentext>
<sentencetext>It seems to me that a transfer oriented architecture is conceptually very easy to parallelize.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162106</id>
	<title>Re:That instruction is ..........</title>
	<author>mwvdlee</author>
	<datestamp>1258664220000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>It's got only one instruction.<nobr> <wbr></nobr>...and the first parameter to that instruction controls what the instruction does with the rest of the parameters.</p><p>(p.s. I wish this was just a joke, but this is pretty much what it seems to be doing)</p></htmltext>
<tokenext>It 's got only one instruction .
...and the first parameter to that instruction controls what the instruction does with the rest of the parameters. ( p.s .
I wish this was just a joke , but this is pretty much what it seems to be doing )</tokentext>
<sentencetext>It's got only one instruction.
...and the first parameter to that instruction controls what the instruction does with the rest of the parameters.(p.s.
I wish this was just a joke, but this is pretty much what it seems to be doing)</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166584</id>
	<title>Re:nihilist</title>
	<author>shutdown -p now</author>
	<datestamp>1258637520000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Personally, I prefer my own Nirvana programming language: it reduces all instructions to an infinite loop.</p></htmltext>
<tokenext>Personally , I prefer my own Nirvana programming language : it reduces all instructions to an infinite loop .</tokentext>
<sentencetext>Personally, I prefer my own Nirvana programming language: it reduces all instructions to an infinite loop.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161388</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30171314</id>
	<title>I also did a TTA fun design</title>
	<author>John Bayko</author>
	<datestamp>1258733760000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I liked the idea and tried doing a design of my own. The thing I didn't like was that you now split up an operation into multiple instructions which couldn't operate concurrently, and I couldn't see how that could be sped up given instruction bus speed limits.</p><p>What I figured was to make the functional units more complex, so instead of having two inputs (left and right operand, implicit function), they'd also take an op code. This meant that I could reduce the number of addresses enough that a single move instruction could be packed into one byte. I don't recall for sure, but I think I used two bits to indicate the bus the move operated on, so you could get three moves happening at once (I think the last 2-bit pattern was reserved for special operations, but I don't recall what they were).</p><p>Branches were straightforward, in that the instruction read unit was just another functional unit, with left, right, and op input, you could just transfer the output from a logic/comparator unit to the op input of the instruction read unit to jump to the new (relative, I think) address or not.</p><p>Constants were defined by a special instruction unit operation which would accumulate 1, 2, or 4 subsequent bytes into the output register, ready to be moved elsewhere (as well as regular load/store from memory).</p><p>There was also a dedicated register file, where the op code was the register to read/write. Just in case the functional unit input/output registers weren't adequate.</p><p>I liked this idea because there'd be no speed penalty - in fact, a typical "regular" instruction would only be 3 bytes, so with the same input bottleneck it could even be faster.</p><p>It didn't get beyond a high level block diagram and instruction/unit descriptions. I'm sure I have a copy of it somewhere, but it got lost in a move (ironically).</p></htmltext>
<tokenext>I liked the idea and tried doing a design of my own .
The thing I did n't like was that you now split up an operation into multiple instructions which could n't operate concurrently , and I could n't see how that could be sped up given instruction bus speed limits.What I figured was to make the functional units more complex , so instead of having two inputs ( left and right operand , implicit function ) , they 'd also take an op code .
This meant that I could reduce the number of addresses enough that a single move instruction could be packed into one byte .
I do n't recall for sure , but I think I used two bits to indicate the bus the move operated on , so you could get three moves happening at once ( I think the last 2-bit pattern was reserved for special operations , but I do n't recall what they were ) .Branches were straightforward , in that the instruction read unit was just another functional unit , with left , right , and op input , you could just transfer the output from a logic/comparator unit to the op input of the instruction read unit to jump to the new ( relative , I think ) address or not.Constants were defined by a special instruction unit operation which would accumulate 1 , 2 , or 4 subsequent bytes into the output register , ready to be moved elsewhere ( as well as regular load/store from memory ) .There was also a dedicated register file , where the op code was the register to read/write .
Just in case the functional unit input/output registers were n't adequate.I liked this idea because there 'd be no speed penalty - in fact , a typical " regular " instruction would only be 3 bytes , so with the same input bottleneck it could even be faster.It did n't get beyond a high level block diagram and instruction/unit descriptions .
I 'm sure I have a copy of it somewhere , but it got lost in a move ( ironically ) .</tokentext>
<sentencetext>I liked the idea and tried doing a design of my own.
The thing I didn't like was that you now split up an operation into multiple instructions which couldn't operate concurrently, and I couldn't see how that could be sped up given instruction bus speed limits.What I figured was to make the functional units more complex, so instead of having two inputs (left and right operand, implicit function), they'd also take an op code.
This meant that I could reduce the number of addresses enough that a single move instruction could be packed into one byte.
I don't recall for sure, but I think I used two bits to indicate the bus the move operated on, so you could get three moves happening at once (I think the last 2-bit pattern was reserved for special operations, but I don't recall what they were).Branches were straightforward, in that the instruction read unit was just another functional unit, with left, right, and op input, you could just transfer the output from a logic/comparator unit to the op input of the instruction read unit to jump to the new (relative, I think) address or not.Constants were defined by a special instruction unit operation which would accumulate 1, 2, or 4 subsequent bytes into the output register, ready to be moved elsewhere (as well as regular load/store from memory).There was also a dedicated register file, where the op code was the register to read/write.
Just in case the functional unit input/output registers weren't adequate.I liked this idea because there'd be no speed penalty - in fact, a typical "regular" instruction would only be 3 bytes, so with the same input bottleneck it could even be faster.It didn't get beyond a high level block diagram and instruction/unit descriptions.
I'm sure I have a copy of it somewhere, but it got lost in a move (ironically).</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164910</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164622</id>
	<title>Re:What's the one instruction?</title>
	<author>Anonymous</author>
	<datestamp>1258628820000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>sudo get me sandwich</p></htmltext>
<tokenext>sudo get me sandwich</tokentext>
<sentencetext>sudo get me sandwich</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161626</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161848</id>
	<title>Re:GOTO ...</title>
	<author>nschubach</author>
	<datestamp>1258663320000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>goto:<br>goto goto</p><p>?</p></htmltext>
<tokenext>goto : goto goto ?</tokentext>
<sentencetext>goto:goto goto?</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162792</id>
	<title>Re:nihilist</title>
	<author>krkoch</author>
	<datestamp>1258623360000</datestamp>
	<modclass>Funny</modclass>
	<modscore>2</modscore>
	<htmltext>Or just the instruction KAH: Push the status register to stack and proceed to kill all humans.</htmltext>
<tokenext>Or just the instruction KAH : Push the status register to stack and proceed to kill all humans .</tokentext>
<sentencetext>Or just the instruction KAH: Push the status register to stack and proceed to kill all humans.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161388</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162090</id>
	<title>One command?</title>
	<author>HockeyPuck</author>
	<datestamp>1258664160000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>Reminds me of this old saying, </p><p><div class="quote"><p>"Every program can be reduced by one instruction, and every program has at least one bug. Therefore, any program can be reduced to one instruction which doesn't work."</p></div><p>I just wish I knew who came up with it.</p></div>
	</htmltext>
<tokenext>Reminds me of this old saying , " Every program can be reduced by one instruction , and every program has at least one bug .
Therefore , any program can be reduced to one instruction which does n't work .
" I just wish I knew who came up with it .</tokentext>
<sentencetext>Reminds me of this old saying, "Every program can be reduced by one instruction, and every program has at least one bug.
Therefore, any program can be reduced to one instruction which doesn't work.
"I just wish I knew who came up with it.
	</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161428</id>
	<title>Good-bye Python!!!</title>
	<author>dmbasso</author>
	<datestamp>1258662060000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Programming in Assembly for this architecture is certainly delightful!!!</p></htmltext>
<tokenext>Programming in Assembly for this architecture is certainly delightful ! !
!</tokentext>
<sentencetext>Programming in Assembly for this architecture is certainly delightful!!
!</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161410</id>
	<title>He's Building a One-Der, Stop Him</title>
	<author>Anonymous</author>
	<datestamp>1258662060000</datestamp>
	<modclass>Funny</modclass>
	<modscore>5</modscore>
	<htmltext>Everyone attack him before he wins this round of Age of Empires.  Quickly, he's probably low on resources right now.</htmltext>
<tokenext>Everyone attack him before he wins this round of Age of Empires .
Quickly , he 's probably low on resources right now .</tokentext>
<sentencetext>Everyone attack him before he wins this round of Age of Empires.
Quickly, he's probably low on resources right now.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168646</id>
	<title>Just moves complexity, doesn't eliminate it</title>
	<author>Anonymous</author>
	<datestamp>1258658100000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>All this does is move the complexity of the instruction decoding from the processor to the address decoders.</p></htmltext>
<tokenext>All this does is move the complexity of the instruction decoding from the processor to the address decoders .</tokentext>
<sentencetext>All this does is move the complexity of the instruction decoding from the processor to the address decoders.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162120</id>
	<title>And now on stage...</title>
	<author>Anonymous</author>
	<datestamp>1258664280000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The Oneder(pronounced oneeder).  Woops, joke lost on geek crowd that probably never saw the movie.</htmltext>
<tokenext>The Oneder ( pronounced oneeder ) .
Woops , joke lost on geek crowd that probably never saw the movie .</tokentext>
<sentencetext>The Oneder(pronounced oneeder).
Woops, joke lost on geek crowd that probably never saw the movie.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166312</id>
	<title>Re:Not new, and not too useful</title>
	<author>SharpFang</author>
	<datestamp>1258636140000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>That's not this approach. It's "memory-map every single operation, as input register/result register." It's really a CISC except mnemonics and data share the same namespace. There's no separation for command and arguments, all arguments are pointers (if you want a fixed value, you must pick it from a range of memory that just produces all possible values) and all commands are in fact "magic registers".</p></htmltext>
<tokenext>That 's not this approach .
It 's " memory-map every single operation , as input register/result register .
" It 's really a CISC except mnemonics and data share the same namespace .
There 's no separation for command and arguments , all arguments are pointers ( if you want a fixed value , you must pick it from a range of memory that just produces all possible values ) and all commands are in fact " magic registers " .</tokentext>
<sentencetext>That's not this approach.
It's "memory-map every single operation, as input register/result register.
" It's really a CISC except mnemonics and data share the same namespace.
There's no separation for command and arguments, all arguments are pointers (if you want a fixed value, you must pick it from a range of memory that just produces all possible values) and all commands are in fact "magic registers".</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161782</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162500</id>
	<title>Re: Computer architecture</title>
	<author>JeffreyDanielRubard</author>
	<datestamp>1258622460000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>What what?</htmltext>
<tokenext>What what ?</tokentext>
<sentencetext>What what?</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161782</id>
	<title>Not new, and not too useful</title>
	<author>Animats</author>
	<datestamp>1258663140000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>5</modscore>
	<htmltext><p>
That's an <a href="http://en.wikipedia.org/wiki/One\_instruction\_set\_computer" title="wikipedia.org">old idea.</a> [wikipedia.org] The classic "one instruction" is "subtract, store, and branch if negative".  This works,
but the instructions are rather big, since each has both an operand address and a branch address.
</p><p>
Once you have your one instruction, you need a macroassembler, because you're going to be generating long code sequences for simple operations like "call".  Then you write the subroutine library, for shifting, multiplication, division, etc.
</p><p>
It's a lose on performance.  It's a lose on code density.  And the guy needed a 1,000,000 gate FPGA to implement it, which is huge for what he's doing.   Chuck Moore's <a href="http://www.ultratechnology.com/chips.htm" title="ultratechnology.com">original Forth chip, from 1985</a> [ultratechnology.com] had less than 4,000 gates, and delivered good performance, with one Forth word executed per clock.</p></htmltext>
<tokenext>That 's an old idea .
[ wikipedia.org ] The classic " one instruction " is " subtract , store , and branch if negative " .
This works , but the instructions are rather big , since each has both an operand address and a branch address .
Once you have your one instruction , you need a macroassembler , because you 're going to be generating long code sequences for simple operations like " call " .
Then you write the subroutine library , for shifting , multiplication , division , etc .
It 's a lose on performance .
It 's a lose on code density .
And the guy needed a 1,000,000 gate FPGA to implement it , which is huge for what he 's doing .
Chuck Moore 's original Forth chip , from 1985 [ ultratechnology.com ] had less than 4,000 gates , and delivered good performance , with one Forth word executed per clock .</tokentext>
<sentencetext>
That's an old idea.
[wikipedia.org] The classic "one instruction" is "subtract, store, and branch if negative".
This works,
but the instructions are rather big, since each has both an operand address and a branch address.
Once you have your one instruction, you need a macroassembler, because you're going to be generating long code sequences for simple operations like "call".
Then you write the subroutine library, for shifting, multiplication, division, etc.
It's a lose on performance.
It's a lose on code density.
And the guy needed a 1,000,000 gate FPGA to implement it, which is huge for what he's doing.
Chuck Moore's original Forth chip, from 1985 [ultratechnology.com] had less than 4,000 gates, and delivered good performance, with one Forth word executed per clock.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161728</id>
	<title>Re:That instruction is ..........</title>
	<author>MozeeToby</author>
	<datestamp>1258662960000</datestamp>
	<modclass>Funny</modclass>
	<modscore>2</modscore>
	<htmltext><p>Unless of course, the ultimate question really is 'What is 6 times 9?' as some people believe (meaning 42 is base 13 for some unknown reason).  Which would of course make the ultimate instruction 0x36.</p></htmltext>
<tokenext>Unless of course , the ultimate question really is 'What is 6 times 9 ?
' as some people believe ( meaning 42 is base 13 for some unknown reason ) .
Which would of course make the ultimate instruction 0x36 .</tokentext>
<sentencetext>Unless of course, the ultimate question really is 'What is 6 times 9?
' as some people believe (meaning 42 is base 13 for some unknown reason).
Which would of course make the ultimate instruction 0x36.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163912</id>
	<title>Re:AAA AA  A A</title>
	<author>Anonymous</author>
	<datestamp>1258626720000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>1</modscore>
	<htmltext><p>Ah, and here's the programmer's manual: <a href="http://uncyclopedia.wikia.com/wiki/AAAAAAAAA!" title="wikia.com" rel="nofollow">clicky</a> [wikia.com] </p></htmltext>
<tokenext>Ah , and here 's the programmer 's manual : clicky [ wikia.com ]</tokentext>
<sentencetext>Ah, and here's the programmer's manual: clicky [wikia.com] </sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161732</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161714</id>
	<title>Not the Ultimate RISC Architecture</title>
	<author>fm6</author>
	<datestamp>1258662960000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>That would be the system with no instructions at all!</p></htmltext>
<tokenext>That would be the system with no instructions at all !</tokentext>
<sentencetext>That would be the system with no instructions at all!</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162548</id>
	<title>The first language I ever saw was GOTO only</title>
	<author>Anonymous</author>
	<datestamp>1258622580000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>The language of naughty schoolboys was goto-only.
However, it never fulfilled on its promise of naked
chicks if you turned to page 69.  Some of the programs
written in said language were, however, quite humerous
and complex.  You could implement loops in that language
of course, and perhaps even keep an idiot busy for hours.
I'm not sure if it was Turing complete though.</p></htmltext>
<tokenext>The language of naughty schoolboys was goto-only .
However , it never fulfilled on its promise of naked chicks if you turned to page 69 .
Some of the programs written in said language were , however , quite humerous and complex .
You could implement loops in that language of course , and perhaps even keep an idiot busy for hours .
I 'm not sure if it was Turing complete though .</tokentext>
<sentencetext>The language of naughty schoolboys was goto-only.
However, it never fulfilled on its promise of naked
chicks if you turned to page 69.
Some of the programs
written in said language were, however, quite humerous
and complex.
You could implement loops in that language
of course, and perhaps even keep an idiot busy for hours.
I'm not sure if it was Turing complete though.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30218474</id>
	<title>Re:Cheating?</title>
	<author>jtgd</author>
	<datestamp>1259056380000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>It would be separate instructions on a RISC machine, but not a traditional CISC machine.<br>

This is a One Instruction CISC (although that seems like an oxymoron)</htmltext>
<tokenext>It would be separate instructions on a RISC machine , but not a traditional CISC machine .
This is a One Instruction CISC ( although that seems like an oxymoron )</tokentext>
<sentencetext>It would be separate instructions on a RISC machine, but not a traditional CISC machine.
This is a One Instruction CISC (although that seems like an oxymoron)</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161416</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161530</id>
	<title>Wrong part number in summary</title>
	<author>Anonymous</author>
	<datestamp>1258662420000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>5</modscore>
	<htmltext><p>It's XC3S1000, not XS3C1000. Been working with these parts too long...</p></htmltext>
<tokenext>It 's XC3S1000 , not XS3C1000 .
Been working with these parts too long.. .</tokentext>
<sentencetext>It's XC3S1000, not XS3C1000.
Been working with these parts too long...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166330</id>
	<title>A machine with just one instruction...</title>
	<author>Fross</author>
	<datestamp>1258636200000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Would anyone like any toast?</p></htmltext>
<tokenext>Would anyone like any toast ?</tokentext>
<sentencetext>Would anyone like any toast?</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162798</id>
	<title>Re:if the instruction is NAND</title>
	<author>SpazmodeusG</author>
	<datestamp>1258623360000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>That's absolutely true. Anyone who has studied CPU logic knows that the CPU is made of NAND gates which can be arranged to make any other gate. A NAND instruction which takes 2 addresses of 2 different bits (has to be bitwise not bytewise) and stores the result can do anything.<br> <br>
One thing i don't get is why it hasn't been done? The wikipedia article on the one instruction computer doesn't list a bitwise AND instruction as being one of the possible instructions for a one instruction computer.<br> <br>
<a href="http://en.wikipedia.org/wiki/One\_instruction\_set\_computer" title="wikipedia.org">http://en.wikipedia.org/wiki/One\_instruction\_set\_computer</a> [wikipedia.org] <br> <br>
But the fact is simple NAND instuctions can do anything.</htmltext>
<tokenext>That 's absolutely true .
Anyone who has studied CPU logic knows that the CPU is made of NAND gates which can be arranged to make any other gate .
A NAND instruction which takes 2 addresses of 2 different bits ( has to be bitwise not bytewise ) and stores the result can do anything .
One thing i do n't get is why it has n't been done ?
The wikipedia article on the one instruction computer does n't list a bitwise AND instruction as being one of the possible instructions for a one instruction computer .
http : //en.wikipedia.org/wiki/One \ _instruction \ _set \ _computer [ wikipedia.org ] But the fact is simple NAND instuctions can do anything .</tokentext>
<sentencetext>That's absolutely true.
Anyone who has studied CPU logic knows that the CPU is made of NAND gates which can be arranged to make any other gate.
A NAND instruction which takes 2 addresses of 2 different bits (has to be bitwise not bytewise) and stores the result can do anything.
One thing i don't get is why it hasn't been done?
The wikipedia article on the one instruction computer doesn't list a bitwise AND instruction as being one of the possible instructions for a one instruction computer.
http://en.wikipedia.org/wiki/One\_instruction\_set\_computer [wikipedia.org]  
But the fact is simple NAND instuctions can do anything.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161828</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30165400</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258631940000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Yes!  It's just another thing about 42 that makes it... that much more mysterious.</p></htmltext>
<tokenext>Yes !
It 's just another thing about 42 that makes it... that much more mysterious .</tokentext>
<sentencetext>Yes!
It's just another thing about 42 that makes it... that much more mysterious.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161902</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168594</id>
	<title>Re:That instruction is ..........</title>
	<author>XDirtypunkX</author>
	<datestamp>1258657200000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Low-level? You only need one button and a good sense of rhythm.</p></htmltext>
<tokenext>Low-level ?
You only need one button and a good sense of rhythm .</tokentext>
<sentencetext>Low-level?
You only need one button and a good sense of rhythm.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161974</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168262</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258653780000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>How do you figure that? The instruction format is pretty straight forward:

{ condition and mask} { source functional unit } { destination functional unit }

So I'm not following what you mean wrt to "first parameter to the instruction? Did you read the article?</htmltext>
<tokenext>How do you figure that ?
The instruction format is pretty straight forward : { condition and mask } { source functional unit } { destination functional unit } So I 'm not following what you mean wrt to " first parameter to the instruction ?
Did you read the article ?</tokentext>
<sentencetext>How do you figure that?
The instruction format is pretty straight forward:

{ condition and mask} { source functional unit } { destination functional unit }

So I'm not following what you mean wrt to "first parameter to the instruction?
Did you read the article?</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162106</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164148</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258627320000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>On the Z80 it's load HL register pair from immediate address/LD HL,(nn), which isn't interesting at all. I call shenanigans.</htmltext>
<tokenext>On the Z80 it 's load HL register pair from immediate address/LD HL , ( nn ) , which is n't interesting at all .
I call shenanigans .</tokentext>
<sentencetext>On the Z80 it's load HL register pair from immediate address/LD HL,(nn), which isn't interesting at all.
I call shenanigans.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161902</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162852</id>
	<title>Geez, History Repeats Itself</title>
	<author>CAOgdin</author>
	<datestamp>1258623660000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext>I invented this and published it more than 30 years ago, during the early debate between CISC and RISC microprocessors.  It was in the (now defunct) "Modern Data" magazine, in my column "Carol's Microcosm."

It's an obvious solution for any computer programmer who understands hardware logic.</htmltext>
<tokenext>I invented this and published it more than 30 years ago , during the early debate between CISC and RISC microprocessors .
It was in the ( now defunct ) " Modern Data " magazine , in my column " Carol 's Microcosm .
" It 's an obvious solution for any computer programmer who understands hardware logic .</tokentext>
<sentencetext>I invented this and published it more than 30 years ago, during the early debate between CISC and RISC microprocessors.
It was in the (now defunct) "Modern Data" magazine, in my column "Carol's Microcosm.
"

It's an obvious solution for any computer programmer who understands hardware logic.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161902</id>
	<title>Re:That instruction is ..........</title>
	<author>Anonymous</author>
	<datestamp>1258663500000</datestamp>
	<modclass>Funny</modclass>
	<modscore>2</modscore>
	<htmltext><p>Appropriate that the ultimate instruction would also be a wildcard (*) in ASCII.</p><p>And speaking of your drums, on Apple II, it's rotate accumulator left, the ROL instruction.</p><p>How curious.</p></htmltext>
<tokenext>Appropriate that the ultimate instruction would also be a wildcard ( * ) in ASCII.And speaking of your drums , on Apple II , it 's rotate accumulator left , the ROL instruction.How curious .</tokentext>
<sentencetext>Appropriate that the ultimate instruction would also be a wildcard (*) in ASCII.And speaking of your drums, on Apple II, it's rotate accumulator left, the ROL instruction.How curious.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166752</id>
	<title>Re:Ummmm</title>
	<author>osu-neko</author>
	<datestamp>1258638600000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The problem with the 90s RISC vs. CISC thing was that it was based on what turned out to be a false dilemma.  Today's processors are both.  They're arguably closer to RISC at the core, but the instruction sets haven't gotten any less CISC from the programmer's point of view, indeed more CISC than ever, leading to the apparently (but only apparently) paradoxical fact that a modern processor is more RISC-y than those 90s RISC chips AND more CISC-y than those 90s CISC chips.  Trying to classify a modern processor as either is just continuing the 90s misconception that these design concepts were irreconcilable, when in fact what happened was clever engineers looked at both ideas and said, "yes, that's a great idea" and implemented both at once.</htmltext>
<tokenext>The problem with the 90s RISC vs. CISC thing was that it was based on what turned out to be a false dilemma .
Today 's processors are both .
They 're arguably closer to RISC at the core , but the instruction sets have n't gotten any less CISC from the programmer 's point of view , indeed more CISC than ever , leading to the apparently ( but only apparently ) paradoxical fact that a modern processor is more RISC-y than those 90s RISC chips AND more CISC-y than those 90s CISC chips .
Trying to classify a modern processor as either is just continuing the 90s misconception that these design concepts were irreconcilable , when in fact what happened was clever engineers looked at both ideas and said , " yes , that 's a great idea " and implemented both at once .</tokentext>
<sentencetext>The problem with the 90s RISC vs. CISC thing was that it was based on what turned out to be a false dilemma.
Today's processors are both.
They're arguably closer to RISC at the core, but the instruction sets haven't gotten any less CISC from the programmer's point of view, indeed more CISC than ever, leading to the apparently (but only apparently) paradoxical fact that a modern processor is more RISC-y than those 90s RISC chips AND more CISC-y than those 90s CISC chips.
Trying to classify a modern processor as either is just continuing the 90s misconception that these design concepts were irreconcilable, when in fact what happened was clever engineers looked at both ideas and said, "yes, that's a great idea" and implemented both at once.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161744</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162876</id>
	<title>Re:GOTO ...</title>
	<author>Anonymous</author>
	<datestamp>1258623720000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>"Where do you want to go to today?"</p></htmltext>
<tokenext>" Where do you want to go to today ?
"</tokentext>
<sentencetext>"Where do you want to go to today?
"</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161744</id>
	<title>Ummmm</title>
	<author>Anonymous</author>
	<datestamp>1258663020000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>1</modscore>
	<htmltext><p>"The advantages of RISC are well known -- simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution."</p><p>Is it just me, or does this sound like RISC fanboyism from the 1990s? The "advantages" of RISC are not nearly so clear these days. Indeed, it is getting rather hard to find real RISC chips. While there are chips based on RISC ISA idea (like being load/store and such), they are not RISC. RISC is about having few instructions and instructions that are simple and only do one thing. Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.</p><p>These days complex processors are the norm. They have special instructions for special things and that seems to work well. RISC is just not very common, even in systems with a RISC heritage.</p><p>I'm just not seeing what this processor is supposed to accomplish, especially being on an FPGA. If you can implement a CPU to do what you need on an FPGA, you can probably implement a dedicated solution on the FPGA that is faster. That is rather the idea of an FPGA over a CPU. You can implement things in hardware that are faster.</p></htmltext>
<tokenext>" The advantages of RISC are well known -- simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds , more registers , and pipelining to provide the appearance of single-cycle execution .
" Is it just me , or does this sound like RISC fanboyism from the 1990s ?
The " advantages " of RISC are not nearly so clear these days .
Indeed , it is getting rather hard to find real RISC chips .
While there are chips based on RISC ISA idea ( like being load/store and such ) , they are not RISC .
RISC is about having few instructions and instructions that are simple and only do one thing .
Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.These days complex processors are the norm .
They have special instructions for special things and that seems to work well .
RISC is just not very common , even in systems with a RISC heritage.I 'm just not seeing what this processor is supposed to accomplish , especially being on an FPGA .
If you can implement a CPU to do what you need on an FPGA , you can probably implement a dedicated solution on the FPGA that is faster .
That is rather the idea of an FPGA over a CPU .
You can implement things in hardware that are faster .</tokentext>
<sentencetext>"The advantages of RISC are well known -- simplifying the CPU core by reducing the complexity of the instruction set allows faster speeds, more registers, and pipelining to provide the appearance of single-cycle execution.
"Is it just me, or does this sound like RISC fanboyism from the 1990s?
The "advantages" of RISC are not nearly so clear these days.
Indeed, it is getting rather hard to find real RISC chips.
While there are chips based on RISC ISA idea (like being load/store and such), they are not RISC.
RISC is about having few instructions and instructions that are simple and only do one thing.
Those concepts are pretty much thrown out when you start having SIMD units on the chip and such.These days complex processors are the norm.
They have special instructions for special things and that seems to work well.
RISC is just not very common, even in systems with a RISC heritage.I'm just not seeing what this processor is supposed to accomplish, especially being on an FPGA.
If you can implement a CPU to do what you need on an FPGA, you can probably implement a dedicated solution on the FPGA that is faster.
That is rather the idea of an FPGA over a CPU.
You can implement things in hardware that are faster.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162126</id>
	<title>According to MS the instruction is</title>
	<author>KiwiCanuck</author>
	<datestamp>1258664280000</datestamp>
	<modclass>Funny</modclass>
	<modscore>3</modscore>
	<htmltext>nop</htmltext>
<tokenext>nop</tokentext>
<sentencetext>nop</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30168638</id>
	<title>I've done this for a while</title>
	<author>ewertz</author>
	<datestamp>1258657980000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>My programs have just one instruction -- ESM (Execute State Machine).  The instruction is exactly the length of my program.</htmltext>
<tokenext>My programs have just one instruction -- ESM ( Execute State Machine ) .
The instruction is exactly the length of my program .</tokentext>
<sentencetext>My programs have just one instruction -- ESM (Execute State Machine).
The instruction is exactly the length of my program.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30186130</id>
	<title>Re: nihilist - Marklar</title>
	<author>fahrbot-bot</author>
	<datestamp>1258830600000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><blockquote><div><p>A language that realizes that ultimately all things are futile and irrelevant, thus allowing all instructions to be reduced to a no-op.</p></div>
</blockquote><p>
<a href="http://www.urbandictionary.com/define.php?term=marklar" title="urbandictionary.com">Marklar:</a> [urbandictionary.com]
"You see, young marklar. Those marklars don't care about marklar marklar. They just want to take your marklar and marklar their own marklar. The only marklar for this is to marklar."</p></div>
	</htmltext>
<tokenext>A language that realizes that ultimately all things are futile and irrelevant , thus allowing all instructions to be reduced to a no-op .
Marklar : [ urbandictionary.com ] " You see , young marklar .
Those marklars do n't care about marklar marklar .
They just want to take your marklar and marklar their own marklar .
The only marklar for this is to marklar .
"</tokentext>
<sentencetext>A language that realizes that ultimately all things are futile and irrelevant, thus allowing all instructions to be reduced to a no-op.
Marklar: [urbandictionary.com]
"You see, young marklar.
Those marklars don't care about marklar marklar.
They just want to take your marklar and marklar their own marklar.
The only marklar for this is to marklar.
"
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161388</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161778</id>
	<title>One-der peripherals</title>
	<author>ZipK</author>
	<datestamp>1258663140000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Is there an optional one-way infinite tape drive?</htmltext>
<tokenext>Is there an optional one-way infinite tape drive ?</tokentext>
<sentencetext>Is there an optional one-way infinite tape drive?</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30165860</id>
	<title>Re:Ummmm</title>
	<author>gbelteshazzar</author>
	<datestamp>1258634040000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>RISC is definately the way these days, even if things look CISC from the outside, internally the best way is to use components that are simpler as they are much easier to understand and optimise, so CISC architectures end up deconstructing their instructions anyway.

RISC isn't just about reducing the instruction set, but about providing less complex instructions that can be implemented more efficiently, although there is one instruction I'd argue that this is a CISC architecture.</htmltext>
<tokenext>RISC is definately the way these days , even if things look CISC from the outside , internally the best way is to use components that are simpler as they are much easier to understand and optimise , so CISC architectures end up deconstructing their instructions anyway .
RISC is n't just about reducing the instruction set , but about providing less complex instructions that can be implemented more efficiently , although there is one instruction I 'd argue that this is a CISC architecture .</tokentext>
<sentencetext>RISC is definately the way these days, even if things look CISC from the outside, internally the best way is to use components that are simpler as they are much easier to understand and optimise, so CISC architectures end up deconstructing their instructions anyway.
RISC isn't just about reducing the instruction set, but about providing less complex instructions that can be implemented more efficiently, although there is one instruction I'd argue that this is a CISC architecture.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161744</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162320</id>
	<title>Re:Can be a bit tricky to program...</title>
	<author>Chris Burke</author>
	<datestamp>1258621800000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>So...  how did you encode what operation the ALU should perform?  And wouldn't that then be the ISA?  Couldn't you then make a "one-instruction microprocessor" where the only instruction is "move bytes to x86 processor instruction cache"?<nobr> <wbr></nobr>;)</p><p>Or was each possible ALU operation a different memory-mapped address?  Was writing the operands to the addresses what caused the operation, or did you have to write to a "do-it" ?</p><p>Not that making such a processor isn't cool.  Cus it's cool.  Making just about any kind of processor in school is cool.<nobr> <wbr></nobr>:)</p><p>Just when I read "one instruction processor" I was thinking of something more traditional, where instructions map to execution units.  So like a machine where the only instruction is NAND with memory arguments.  Now <i>that</i> would be a bitch to program.<nobr> <wbr></nobr>;)</p></htmltext>
<tokenext>So... how did you encode what operation the ALU should perform ?
And would n't that then be the ISA ?
Could n't you then make a " one-instruction microprocessor " where the only instruction is " move bytes to x86 processor instruction cache " ?
; ) Or was each possible ALU operation a different memory-mapped address ?
Was writing the operands to the addresses what caused the operation , or did you have to write to a " do-it " ? Not that making such a processor is n't cool .
Cus it 's cool .
Making just about any kind of processor in school is cool .
: ) Just when I read " one instruction processor " I was thinking of something more traditional , where instructions map to execution units .
So like a machine where the only instruction is NAND with memory arguments .
Now that would be a bitch to program .
; )</tokentext>
<sentencetext>So...  how did you encode what operation the ALU should perform?
And wouldn't that then be the ISA?
Couldn't you then make a "one-instruction microprocessor" where the only instruction is "move bytes to x86 processor instruction cache"?
;)Or was each possible ALU operation a different memory-mapped address?
Was writing the operands to the addresses what caused the operation, or did you have to write to a "do-it" ?Not that making such a processor isn't cool.
Cus it's cool.
Making just about any kind of processor in school is cool.
:)Just when I read "one instruction processor" I was thinking of something more traditional, where instructions map to execution units.
So like a machine where the only instruction is NAND with memory arguments.
Now that would be a bitch to program.
;)</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161468</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163090</id>
	<title>NOR or NAND?</title>
	<author>karstdiver</author>
	<datestamp>1258624380000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>All Boolean logic functions can be implemented with just a NOR or NAND.  Add a conditional branch and a move (ok- more than one instruction now) and you have a general purpose computer.</htmltext>
<tokenext>All Boolean logic functions can be implemented with just a NOR or NAND .
Add a conditional branch and a move ( ok- more than one instruction now ) and you have a general purpose computer .</tokentext>
<sentencetext>All Boolean logic functions can be implemented with just a NOR or NAND.
Add a conditional branch and a move (ok- more than one instruction now) and you have a general purpose computer.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30167072</id>
	<title>well allow me to retort..</title>
	<author>hldn</author>
	<datestamp>1258640820000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>- RISC architecture is gonna change everything.<br>- Yeah. RISC is good.</p><p>QED</p></htmltext>
<tokenext>- RISC architecture is gon na change everything.- Yeah .
RISC is good.QED</tokentext>
<sentencetext>- RISC architecture is gonna change everything.- Yeah.
RISC is good.QED</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161790</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30175686</id>
	<title>Re:Can be a bit tricky to program...</title>
	<author>Blue Lozenge</author>
	<datestamp>1258749240000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>It sounds to me like you just moved the instruction opcodes into the address operand.</htmltext>
<tokenext>It sounds to me like you just moved the instruction opcodes into the address operand .</tokentext>
<sentencetext>It sounds to me like you just moved the instruction opcodes into the address operand.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161468</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163022</id>
	<title>Re:"ideal for One-Der"?</title>
	<author>Anonymous</author>
	<datestamp>1258624200000</datestamp>
	<modclass>Funny</modclass>
	<modscore>1</modscore>
	<htmltext><p>And now introducing the O-NEE-DERS</p></htmltext>
<tokenext>And now introducing the O-NEE-DERS</tokentext>
<sentencetext>And now introducing the O-NEE-DERS</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162158</id>
	<title>Re:GOTO ...</title>
	<author>deander2</author>
	<datestamp>1258621260000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>that would be the JMP instruction.  =P</p></htmltext>
<tokenext>that would be the JMP instruction .
= P</tokentext>
<sentencetext>that would be the JMP instruction.
=P</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161626</id>
	<title>What's the one instruction?</title>
	<author>Chris Mattern</author>
	<datestamp>1258662720000</datestamp>
	<modclass>Funny</modclass>
	<modscore>5</modscore>
	<htmltext><p>Why, DWIW (Do What I Want), of course.</p></htmltext>
<tokenext>Why , DWIW ( Do What I Want ) , of course .</tokentext>
<sentencetext>Why, DWIW (Do What I Want), of course.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163532</id>
	<title>Re:That instruction is ..........</title>
	<author>Nethead</author>
	<datestamp>1258625640000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Wow! It's the same as on a VIC-20, wonder why.</p></htmltext>
<tokenext>Wow !
It 's the same as on a VIC-20 , wonder why .</tokentext>
<sentencetext>Wow!
It's the same as on a VIC-20, wonder why.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161902</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162368</id>
	<title>Re:Cheating?</title>
	<author>Talennor</author>
	<datestamp>1258621980000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext><p><div class="quote"><p>So the one instuction is essentially a move command that has multiple modes... Ahem. Isn't that cheating?</p></div><p>Yes, it is cheating.  He basically took the instruction bits of the program and said, "Behold, for they are now address bits!"  With the caveat that the address bits happen to address INSTRUCTIONS.  It's all pretty brain-dead.</p></div>
	</htmltext>
<tokenext>So the one instuction is essentially a move command that has multiple modes... Ahem. Is n't that cheating ? Yes , it is cheating .
He basically took the instruction bits of the program and said , " Behold , for they are now address bits !
" With the caveat that the address bits happen to address INSTRUCTIONS .
It 's all pretty brain-dead .</tokentext>
<sentencetext>So the one instuction is essentially a move command that has multiple modes... Ahem. Isn't that cheating?Yes, it is cheating.
He basically took the instruction bits of the program and said, "Behold, for they are now address bits!
"  With the caveat that the address bits happen to address INSTRUCTIONS.
It's all pretty brain-dead.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161416</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30169186</id>
	<title>Re:Oh my, you'll never believe what I'm about to s</title>
	<author>TheThiefMaster</author>
	<datestamp>1258712280000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I've been mucking about with the idea of building a cpu from logic gates for a while now, and I might have to use a "single instruction" architecture. The registers and inputs and outputs of small function units would all be addressable memory. Technically you could argue that some addresses have instruction meanings as a result, but what the hell. A program would be along the lines of:<br>Move from constant #000 (could be memory loc #000) to increment input 0 (say memory loc #002)<br>Move from memory loc #100 (a real memory location) to add unit input 0 (say memory loc #006)<br>Move from memory loc #101 to add unit input 1 (say memory loc #007)<br>Move from add unit output 0 (say memory loc #008) to memory loc #101<br>Move from increment output 0 (say memory loc #003) to increment input 0 (loc #002)<br>and then a conditional jump to the top on the increment output reaching a value, which I figure would have to be handled by a subtract and a "conditional unit", with the conditional unit returning one input or another depending on yet another input (fed from the subtract), which could then be moved into the PC. Yes, this technically means it does a non-conditional jump to one of two addresses depending on a condition, not a "conditional jump", but that's close enough.</p><p>It would be easy to build due to being so incredibly modular. You could even make it execute two "instructions" per clock or more to make some more traditional instructions take only a single clock cycle, instead of a cycle per input and output.</p></htmltext>
<tokenext>I 've been mucking about with the idea of building a cpu from logic gates for a while now , and I might have to use a " single instruction " architecture .
The registers and inputs and outputs of small function units would all be addressable memory .
Technically you could argue that some addresses have instruction meanings as a result , but what the hell .
A program would be along the lines of : Move from constant # 000 ( could be memory loc # 000 ) to increment input 0 ( say memory loc # 002 ) Move from memory loc # 100 ( a real memory location ) to add unit input 0 ( say memory loc # 006 ) Move from memory loc # 101 to add unit input 1 ( say memory loc # 007 ) Move from add unit output 0 ( say memory loc # 008 ) to memory loc # 101Move from increment output 0 ( say memory loc # 003 ) to increment input 0 ( loc # 002 ) and then a conditional jump to the top on the increment output reaching a value , which I figure would have to be handled by a subtract and a " conditional unit " , with the conditional unit returning one input or another depending on yet another input ( fed from the subtract ) , which could then be moved into the PC .
Yes , this technically means it does a non-conditional jump to one of two addresses depending on a condition , not a " conditional jump " , but that 's close enough.It would be easy to build due to being so incredibly modular .
You could even make it execute two " instructions " per clock or more to make some more traditional instructions take only a single clock cycle , instead of a cycle per input and output .</tokentext>
<sentencetext>I've been mucking about with the idea of building a cpu from logic gates for a while now, and I might have to use a "single instruction" architecture.
The registers and inputs and outputs of small function units would all be addressable memory.
Technically you could argue that some addresses have instruction meanings as a result, but what the hell.
A program would be along the lines of:Move from constant #000 (could be memory loc #000) to increment input 0 (say memory loc #002)Move from memory loc #100 (a real memory location) to add unit input 0 (say memory loc #006)Move from memory loc #101 to add unit input 1 (say memory loc #007)Move from add unit output 0 (say memory loc #008) to memory loc #101Move from increment output 0 (say memory loc #003) to increment input 0 (loc #002)and then a conditional jump to the top on the increment output reaching a value, which I figure would have to be handled by a subtract and a "conditional unit", with the conditional unit returning one input or another depending on yet another input (fed from the subtract), which could then be moved into the PC.
Yes, this technically means it does a non-conditional jump to one of two addresses depending on a condition, not a "conditional jump", but that's close enough.It would be easy to build due to being so incredibly modular.
You could even make it execute two "instructions" per clock or more to make some more traditional instructions take only a single clock cycle, instead of a cycle per input and output.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164910</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161468</id>
	<title>Can be a bit tricky to program...</title>
	<author>nokiator</author>
	<datestamp>1258662180000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>5</modscore>
	<htmltext>I built a single instruction microprocessor at grad school. The only instruction was to move a 32-bit data from one address to another address. All the ALU and I/O functions were memory mapped. For example, you could have an adder where address A was operand #1, address B was operand #2 and address C was the result. Branches were handled through ALU units where the result of the operation changed the instruction pointer for some future instruction. It was very easy to implement and notoriously difficult to program.</htmltext>
<tokenext>I built a single instruction microprocessor at grad school .
The only instruction was to move a 32-bit data from one address to another address .
All the ALU and I/O functions were memory mapped .
For example , you could have an adder where address A was operand # 1 , address B was operand # 2 and address C was the result .
Branches were handled through ALU units where the result of the operation changed the instruction pointer for some future instruction .
It was very easy to implement and notoriously difficult to program .</tokentext>
<sentencetext>I built a single instruction microprocessor at grad school.
The only instruction was to move a 32-bit data from one address to another address.
All the ALU and I/O functions were memory mapped.
For example, you could have an adder where address A was operand #1, address B was operand #2 and address C was the result.
Branches were handled through ALU units where the result of the operation changed the instruction pointer for some future instruction.
It was very easy to implement and notoriously difficult to program.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162958</id>
	<title>Re:Can be a bit tricky to program...</title>
	<author>bigdavex</author>
	<datestamp>1258624020000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>It seems to me that the the distinction between the microprocessor and the ALU is arbitrary.  How is this different than a CPU that comprises address load hardware and ALUs?</p></htmltext>
<tokenext>It seems to me that the the distinction between the microprocessor and the ALU is arbitrary .
How is this different than a CPU that comprises address load hardware and ALUs ?</tokentext>
<sentencetext>It seems to me that the the distinction between the microprocessor and the ALU is arbitrary.
How is this different than a CPU that comprises address load hardware and ALUs?</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161468</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162108</id>
	<title>Re:Ummmm</title>
	<author>Anonymous</author>
	<datestamp>1258664220000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext><p>This isn't true. Modern processors are highly RISCy -- they just have front-ends that translate from CISC ISAs. The last genuinely CISC processor was, I believe, the Pentium (non-pro edition).</p></htmltext>
<tokenext>This is n't true .
Modern processors are highly RISCy -- they just have front-ends that translate from CISC ISAs .
The last genuinely CISC processor was , I believe , the Pentium ( non-pro edition ) .</tokentext>
<sentencetext>This isn't true.
Modern processors are highly RISCy -- they just have front-ends that translate from CISC ISAs.
The last genuinely CISC processor was, I believe, the Pentium (non-pro edition).</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161744</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30170032</id>
	<title>Re:Ummmm</title>
	<author>anss123</author>
	<datestamp>1258725240000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><div class="quote"><p>I'd say it's more the other way around. Even in systems with a CISC ISA (e.g. x86), you tend to find that under the hood the CISC instructions are translated into a series of microops that are then dispatched in a system that is somewhat RISC-like.</p></div><p>Keep in mind that even the ancient 8086 had microcode (aka. instructions that were broken up into simpler instructions) and IIRC the latest Core chips executes more instructions on a 1-to-1 basis than any earlier x86 chips, which arguably makes it more CISC than ever before. There is no clear definition on what CISC is though, it's more like CISC is "not RISC" and RISC is whatever pulls ARM/PPC/MIPS/ALPHA/!x86 under the same umbrella.
</p><p>
To muddle matters the PPC970 chip cracks up instructions and ARM (with thumb) got variable length instructions - just like any good CISC... no wait<nobr> <wbr></nobr>:-)</p></div>
	</htmltext>
<tokenext>I 'd say it 's more the other way around .
Even in systems with a CISC ISA ( e.g .
x86 ) , you tend to find that under the hood the CISC instructions are translated into a series of microops that are then dispatched in a system that is somewhat RISC-like.Keep in mind that even the ancient 8086 had microcode ( aka .
instructions that were broken up into simpler instructions ) and IIRC the latest Core chips executes more instructions on a 1-to-1 basis than any earlier x86 chips , which arguably makes it more CISC than ever before .
There is no clear definition on what CISC is though , it 's more like CISC is " not RISC " and RISC is whatever pulls ARM/PPC/MIPS/ALPHA/ ! x86 under the same umbrella .
To muddle matters the PPC970 chip cracks up instructions and ARM ( with thumb ) got variable length instructions - just like any good CISC... no wait : - )</tokentext>
<sentencetext>I'd say it's more the other way around.
Even in systems with a CISC ISA (e.g.
x86), you tend to find that under the hood the CISC instructions are translated into a series of microops that are then dispatched in a system that is somewhat RISC-like.Keep in mind that even the ancient 8086 had microcode (aka.
instructions that were broken up into simpler instructions) and IIRC the latest Core chips executes more instructions on a 1-to-1 basis than any earlier x86 chips, which arguably makes it more CISC than ever before.
There is no clear definition on what CISC is though, it's more like CISC is "not RISC" and RISC is whatever pulls ARM/PPC/MIPS/ALPHA/!x86 under the same umbrella.
To muddle matters the PPC970 chip cracks up instructions and ARM (with thumb) got variable length instructions - just like any good CISC... no wait :-)
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162174</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162670</id>
	<title>Re:"ideal for One-Der"?</title>
	<author>mattdm</author>
	<datestamp>1258622940000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The sentence from the summary which you're replying to makes more sense in its full context in the article:<blockquote><div><p>Even so, One-Der is imminently usable as it is. Unlike many other FPGA CPU cores, this one is very simple to customize even if you aren't an expert on its internals. Applications that can benefit from custom instruction in hardware -- things like digital signal processing, for example -- are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU.</p></div></blockquote><p>

In other words, it's an ideal starting point for these applications.</p></div>
	</htmltext>
<tokenext>The sentence from the summary which you 're replying to makes more sense in its full context in the article : Even so , One-Der is imminently usable as it is .
Unlike many other FPGA CPU cores , this one is very simple to customize even if you are n't an expert on its internals .
Applications that can benefit from custom instruction in hardware -- things like digital signal processing , for example -- are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU .
In other words , it 's an ideal starting point for these applications .</tokentext>
<sentencetext>The sentence from the summary which you're replying to makes more sense in its full context in the article:Even so, One-Der is imminently usable as it is.
Unlike many other FPGA CPU cores, this one is very simple to customize even if you aren't an expert on its internals.
Applications that can benefit from custom instruction in hardware -- things like digital signal processing, for example -- are ideal for One-Der since you can implement parts of your algorithm in hardware and then easily integrate those parts with the CPU.
In other words, it's an ideal starting point for these applications.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163076</id>
	<title>One instruction to rule them all!</title>
	<author>DarthVain</author>
	<datestamp>1258624380000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>1) "KILL ALL HUMANS!"</p></htmltext>
<tokenext>1 ) " KILL ALL HUMANS !
"</tokentext>
<sentencetext>1) "KILL ALL HUMANS!
"</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166932</id>
	<title>Re:Cheating?</title>
	<author>Nazlfrag</author>
	<datestamp>1258639740000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>I suppose it's cheating. I think it's useful though simply as a backbone for a custom processor, then patch in what you need. You might need an ALU and DSP for a complex project, and an accumulator &amp; bit shifter for a simpler one. This lets you link them to a common bus architecture which could make for easy prototyping.</p></htmltext>
<tokenext>I suppose it 's cheating .
I think it 's useful though simply as a backbone for a custom processor , then patch in what you need .
You might need an ALU and DSP for a complex project , and an accumulator &amp; bit shifter for a simpler one .
This lets you link them to a common bus architecture which could make for easy prototyping .</tokentext>
<sentencetext>I suppose it's cheating.
I think it's useful though simply as a backbone for a custom processor, then patch in what you need.
You might need an ALU and DSP for a complex project, and an accumulator &amp; bit shifter for a simpler one.
This lets you link them to a common bus architecture which could make for easy prototyping.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161416</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161654</id>
	<title>Microblaze</title>
	<author>Anonymous</author>
	<datestamp>1258662780000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>It occurs to me that the Microblaze would be 10 times faster, much easier to program and probably of a similar size.</p></htmltext>
<tokenext>It occurs to me that the Microblaze would be 10 times faster , much easier to program and probably of a similar size .</tokentext>
<sentencetext>It occurs to me that the Microblaze would be 10 times faster, much easier to program and probably of a similar size.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162488</id>
	<title>This is progress?</title>
	<author>pedantic bore</author>
	<datestamp>1258622400000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p> 2009: one million gates, one instruction, RISC, gnarly to program = 10 MIPS. </p><p> 1984: 200,000 gates, gobs of instructions, CISC, easy to program = 10 MIPS. </p><p> We should have more to show for the last twenty-five years in microprocessor design. </p></htmltext>
<tokenext>2009 : one million gates , one instruction , RISC , gnarly to program = 10 MIPS .
1984 : 200,000 gates , gobs of instructions , CISC , easy to program = 10 MIPS .
We should have more to show for the last twenty-five years in microprocessor design .</tokentext>
<sentencetext> 2009: one million gates, one instruction, RISC, gnarly to program = 10 MIPS.
1984: 200,000 gates, gobs of instructions, CISC, easy to program = 10 MIPS.
We should have more to show for the last twenty-five years in microprocessor design. </sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163028</id>
	<title>Re:That instruction is ..........</title>
	<author>pgn674</author>
	<datestamp>1258624200000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><div class="quote"><p>0x2A</p></div><p>Took me a while to see the Hitchhiker reference.<br>
Very interesting, though, that 0x2A is SUB r8 r/m8 in the x86 instruction set. Isn't a Turing difference machine just subtraction with two read/write heads and a linear medium?</p></div>
	</htmltext>
<tokenext>0x2ATook me a while to see the Hitchhiker reference .
Very interesting , though , that 0x2A is SUB r8 r/m8 in the x86 instruction set .
Is n't a Turing difference machine just subtraction with two read/write heads and a linear medium ?</tokentext>
<sentencetext>0x2ATook me a while to see the Hitchhiker reference.
Very interesting, though, that 0x2A is SUB r8 r/m8 in the x86 instruction set.
Isn't a Turing difference machine just subtraction with two read/write heads and a linear medium?
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161674</id>
	<title>Old news</title>
	<author>Al Kossow</author>
	<datestamp>1258662840000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Mike Albaugh did this in 1986<br>Google for<br>urisc macro package  in the net.arch archives.<br>His instruction was "Reverse subtract and skip if borrow"</p></htmltext>
<tokenext>Mike Albaugh did this in 1986Google forurisc macro package in the net.arch archives.His instruction was " Reverse subtract and skip if borrow "</tokentext>
<sentencetext>Mike Albaugh did this in 1986Google forurisc macro package  in the net.arch archives.His instruction was "Reverse subtract and skip if borrow"</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161416</id>
	<title>Cheating?</title>
	<author>Anonymous</author>
	<datestamp>1258662060000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>4</modscore>
	<htmltext>So the one instuction is essentially a move command that has multiple modes... Ahem. Isn't that cheating?

Isn't move considered two instructions already, a load and store? I guess this is really dependent upon how you define what is and isn't an instruction.</htmltext>
<tokenext>So the one instuction is essentially a move command that has multiple modes... Ahem. Is n't that cheating ?
Is n't move considered two instructions already , a load and store ?
I guess this is really dependent upon how you define what is and is n't an instruction .</tokentext>
<sentencetext>So the one instuction is essentially a move command that has multiple modes... Ahem. Isn't that cheating?
Isn't move considered two instructions already, a load and store?
I guess this is really dependent upon how you define what is and isn't an instruction.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30165814</id>
	<title>Re:What's the one instruction?</title>
	<author>Niomosy</author>
	<datestamp>1258633860000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>That instruction can already be found in most females.</p></htmltext>
<tokenext>That instruction can already be found in most females .</tokentext>
<sentencetext>That instruction can already be found in most females.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161626</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162584</id>
	<title>Re:Ummmm</title>
	<author>Dunbal</author>
	<datestamp>1258622700000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><i>Is it just me, or does this sound like RISC fanboyism from the 1990s? </i></p><p>
&nbsp; &nbsp; &nbsp; The good thing about fashion is that if you wait long enough, everything will be in vogue again. I'm just waiting for the day when my crates of punch cards will be in demand by everyone. My great grand-children will surely respect me THEN.</p></htmltext>
<tokenext>Is it just me , or does this sound like RISC fanboyism from the 1990s ?
      The good thing about fashion is that if you wait long enough , everything will be in vogue again .
I 'm just waiting for the day when my crates of punch cards will be in demand by everyone .
My great grand-children will surely respect me THEN .</tokentext>
<sentencetext>Is it just me, or does this sound like RISC fanboyism from the 1990s?
      The good thing about fashion is that if you wait long enough, everything will be in vogue again.
I'm just waiting for the day when my crates of punch cards will be in demand by everyone.
My great grand-children will surely respect me THEN.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161744</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30164050</id>
	<title>Re:I think it's misleading to call it 1 instructio</title>
	<author>Anonymous</author>
	<datestamp>1258627080000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Erm, you know that Memory Mapped devices are in every day use right? That the x86 CPU exports things like the APIC through memory mapping even though it's built-in to the CPU?</p><p>If you have a video card, the card's control registers are memory mapped more likely then not.</p><p>The real problem with alternative CPU architectures is the x86 arch has very good memory consistency, the out-of-order execution units block processing that read results which haven't been calculated yet whereas CPUs like the Alpha do not; this is just great in that you can read 2 numbers, add them, save to memory then read the memory and the read operation may actually return whatever was in the RAM before the add due to deciding that was the easiest operation to do first.</p></htmltext>
<tokenext>Erm , you know that Memory Mapped devices are in every day use right ?
That the x86 CPU exports things like the APIC through memory mapping even though it 's built-in to the CPU ? If you have a video card , the card 's control registers are memory mapped more likely then not.The real problem with alternative CPU architectures is the x86 arch has very good memory consistency , the out-of-order execution units block processing that read results which have n't been calculated yet whereas CPUs like the Alpha do not ; this is just great in that you can read 2 numbers , add them , save to memory then read the memory and the read operation may actually return whatever was in the RAM before the add due to deciding that was the easiest operation to do first .</tokentext>
<sentencetext>Erm, you know that Memory Mapped devices are in every day use right?
That the x86 CPU exports things like the APIC through memory mapping even though it's built-in to the CPU?If you have a video card, the card's control registers are memory mapped more likely then not.The real problem with alternative CPU architectures is the x86 arch has very good memory consistency, the out-of-order execution units block processing that read results which haven't been calculated yet whereas CPUs like the Alpha do not; this is just great in that you can read 2 numbers, add them, save to memory then read the memory and the read operation may actually return whatever was in the RAM before the add due to deciding that was the easiest operation to do first.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162212</parent>
</comment>
<thread>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#thread_09_11_19_1845205_57</id>
	<commentlist>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161464
http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162876
</commentlist>
</thread>
<thread>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#thread_09_11_19_1845205_60</id>
	<commentlist>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161312
http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161728
http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30162630
</commentlist>
</thread>
<thread>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#thread_09_11_19_1845205_33</id>
	<commentlist>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362
http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30166136
</commentlist>
</thread>
<thread>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#thread_09_11_19_1845205_56</id>
	<commentlist>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30161362
http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_11_19_1845205.30163022
</commentlist>
</thread>
<thread>
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