<article>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#article09_05_31_187208</id>
	<title>VHDL or Verilog For Learning FPGAs?</title>
	<author>timothy</author>
	<datestamp>1243794120000</datestamp>
	<htmltext>FlyByPC writes <i>"We're in the first stages of designing a course in programmable devices at the university where I work. The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA. I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++. FPGAs, though, are new to me (although they look very interesting.) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely? (...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?) At this point, I've only seen a little of both languages, so I have no real preference. Any input, especially if you're using one or both in the field, would be very helpful. Thanks, and may all of your K-maps be glitch-free."</i></htmltext>
<tokenext>FlyByPC writes " We 're in the first stages of designing a course in programmable devices at the university where I work .
The course will most likely be centered around various small projects implemented on an FPGA dev board , using a Xilinx Spartan3-series FPGA .
I have a bit of experience working with technologies from 7400-series chips ( designing using schematics ) to 8-bit microcontrollers to C/C + + .
FPGAs , though , are new to me ( although they look very interesting .
) If you were an undergraduate student studying programmable devices ( specifically , FPGAs ) , would you prefer the course be centered on VHDL , Verilog , a little of both , or something else entirely ?
( ...Or is this an eternal , undecidable holy-war question along the lines of ATI/nVidia , AMD/Intel , Coke/Pepsi , etc... ?
) At this point , I 've only seen a little of both languages , so I have no real preference .
Any input , especially if you 're using one or both in the field , would be very helpful .
Thanks , and may all of your K-maps be glitch-free .
"</tokentext>
<sentencetext>FlyByPC writes "We're in the first stages of designing a course in programmable devices at the university where I work.
The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA.
I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++.
FPGAs, though, are new to me (although they look very interesting.
) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely?
(...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?
) At this point, I've only seen a little of both languages, so I have no real preference.
Any input, especially if you're using one or both in the field, would be very helpful.
Thanks, and may all of your K-maps be glitch-free.
"</sentencetext>
</article>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28166313</id>
	<title>Some data</title>
	<author>Anonymous</author>
	<datestamp>1243862100000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>For some empirical data that may be useful:<br><a href="http://www.deepchip.com/items/dvcon07-02.html" title="deepchip.com" rel="nofollow">http://www.deepchip.com/items/dvcon07-02.html</a> [deepchip.com]<br>The results, although two years old, show that Verilog is a bit more widely used.</p><p>I've used both, and I prefer Verilog. Good luck with your course preparation.</p></htmltext>
<tokenext>For some empirical data that may be useful : http : //www.deepchip.com/items/dvcon07-02.html [ deepchip.com ] The results , although two years old , show that Verilog is a bit more widely used.I 've used both , and I prefer Verilog .
Good luck with your course preparation .</tokentext>
<sentencetext>For some empirical data that may be useful:http://www.deepchip.com/items/dvcon07-02.html [deepchip.com]The results, although two years old, show that Verilog is a bit more widely used.I've used both, and I prefer Verilog.
Good luck with your course preparation.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243761360000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>5</modscore>
	<htmltext><p>Having now read through the entirety of the comments on this story, the trend I see is that:<br>A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while<br>B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and<br>C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.</p><p>Based on that review, I'd say teach your students VHDL.  The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.</p></htmltext>
<tokenext>Having now read through the entirety of the comments on this story , the trend I see is that : A ) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine , whileB ) students who learned with Verilog then went on to a career with VHDL , while rarer , think VHDL is a harder language , andC ) students who were forced to take VHDL when it was n't in their career plan hated it , because it was so different than a programming language.Based on that review , I 'd say teach your students VHDL .
The students that learn it and do well in your course will have the easiest time in the industry , and those that hate it probably wo n't become good HDL designers regardless .</tokentext>
<sentencetext>Having now read through the entirety of the comments on this story, the trend I see is that:A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, whileB) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, andC) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.Based on that review, I'd say teach your students VHDL.
The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28164001</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243788960000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I don't believe teaching both languages is really practical. I've been in courses that attempted this (Java and C#) and they fail miserably for the fact that any programmer who understands the concepts behind the language can generally pick up a different syntax/language with a minimum of effort. If, however, they learn only the language and not the concepts behind it's use they'll be doomed to be explicitly taught how to do everything in that language.</p><p>Teach a man to fish, and all that.</p><p>I've used both Verilog and VHDL and largely agree with the top post. VHDL is much more verbose than Verilog and, consequently, is uniquely suited to environments where that is desirable. Verilog is more C-like in both it's "weakly typed" sense (in C you're dealing with taking void * and casting it to something else, in Verilog you're dealing with breaking a bus into bits, etc) as well as syntactically. Verilog will be easier for your students to pick up if your university/college/school's curriculum is C/C++/Java centered.</p></htmltext>
<tokenext>I do n't believe teaching both languages is really practical .
I 've been in courses that attempted this ( Java and C # ) and they fail miserably for the fact that any programmer who understands the concepts behind the language can generally pick up a different syntax/language with a minimum of effort .
If , however , they learn only the language and not the concepts behind it 's use they 'll be doomed to be explicitly taught how to do everything in that language.Teach a man to fish , and all that.I 've used both Verilog and VHDL and largely agree with the top post .
VHDL is much more verbose than Verilog and , consequently , is uniquely suited to environments where that is desirable .
Verilog is more C-like in both it 's " weakly typed " sense ( in C you 're dealing with taking void * and casting it to something else , in Verilog you 're dealing with breaking a bus into bits , etc ) as well as syntactically .
Verilog will be easier for your students to pick up if your university/college/school 's curriculum is C/C + + /Java centered .</tokentext>
<sentencetext>I don't believe teaching both languages is really practical.
I've been in courses that attempted this (Java and C#) and they fail miserably for the fact that any programmer who understands the concepts behind the language can generally pick up a different syntax/language with a minimum of effort.
If, however, they learn only the language and not the concepts behind it's use they'll be doomed to be explicitly taught how to do everything in that language.Teach a man to fish, and all that.I've used both Verilog and VHDL and largely agree with the top post.
VHDL is much more verbose than Verilog and, consequently, is uniquely suited to environments where that is desirable.
Verilog is more C-like in both it's "weakly typed" sense (in C you're dealing with taking void * and casting it to something else, in Verilog you're dealing with breaking a bus into bits, etc) as well as syntactically.
Verilog will be easier for your students to pick up if your university/college/school's curriculum is C/C++/Java centered.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159981</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160959</id>
	<title>If you know what you are doing ...</title>
	<author>BitZtream</author>
	<datestamp>1243762440000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Then the language is almost irrelevant.  A good developer, software or hardware, can use just about anything thrown at them to accomplish the task, given a reference manual for the language.  FPGAs are just another form of programming and should be treated as such.  (Or you could say that software is just an extension of hardware and should be treated as such, doesn't really matter which way it goes).</p><p>So, to answer your question.  At this point in time, for you, which one you use depends more on non-technical issues such as what hardware you're going to be using to do the initial development.  If you can find a Verilog compiler but not a VHDL for the hardware you're going to start with then the question answers itself.  For instance if you were going to use an ATmel FPGA, you're most likely going to be using their workbench and the language it uses (Cant remember off the top of my head which it actually is) as it contains the best integration with the hardware for development and testing purposes.  It would be silly to try to use the other language with an ATmel FPGA unless you already have a large base of components built in that language to port, which if you already had that base set of components, you would already know the answer to the question you ask.</p><p>When you get to the point that which language use you actually matters, you'll be fully aware of it and at that point you'll actually be able to make a decision.  This is true for just about every programming language on the planet, hardware or software.  The language matters a lot less than most programmers think.  The reality of it is, most programmers suck ass, and the reason they are so loudly voiced about 'their' language and all its 'greatness' is because they don't really know how to program, they just know enough to make their preferred language do something useful.  At the extremes of programming its a little different.  If you're talking about writing software for a micro controller with no memory management support and/or tiny amounts ( or no) ram, then using Java would be dumb (even if you had a VM already).  C makes more sense, but with little ram, it may waste too many resources there as well, so you're going to be using assembly in most cases anyway.   When you're working on a Mac, Linux or Windows desktop PC however, those sort of limitations simply don't matter to most apps, so any language will do until you come up with a reason the language won't work.  Since you know very little about the languages involved at this point, you probably can not make a educated choice at this time.  Even when you do start running into limitations, its likely going to be the same for both languages or a compiler issue.  For instance, there is no 'reason' a C# app can not be as fast as an app doing the same thing in assembly though it does happen.  It happens because the compilers used to turn C# into actual executable code that the processor understands in not nearly as effecient at generating machine language as an assembly programmer doing only EXACTLY what it has to do and taking advantages of the way the machine itself works.</p><p>With Verilog and VHDL its all just gates in the end.  At this stage its practically impossible to determine which one will be more effecient for you to use.  You're coding style, your abilities, the quirks of the compilers, the ease of use and understanding of the tools all matter far more than anything else.  You'll see plenty of slashdot posts exclaiming which one is better, but the reality of it is, you won't know which one is better for YOU and YOUR PROJECT until you get some experience.  Unless you plane on laying out your entire game plan, what you are building, how you intend to go about it, what hardware you're using and EVERY other specification about your project, than any advice is just a guess and not even an educated one.  Someone may say 'Use VHDL, it does X, Z, Y, and really is easy to use thanks to feature B'.  Feature B sounds important, so you use VHDL.  Turns out that you never use feature B, and becau</p></htmltext>
<tokenext>Then the language is almost irrelevant .
A good developer , software or hardware , can use just about anything thrown at them to accomplish the task , given a reference manual for the language .
FPGAs are just another form of programming and should be treated as such .
( Or you could say that software is just an extension of hardware and should be treated as such , does n't really matter which way it goes ) .So , to answer your question .
At this point in time , for you , which one you use depends more on non-technical issues such as what hardware you 're going to be using to do the initial development .
If you can find a Verilog compiler but not a VHDL for the hardware you 're going to start with then the question answers itself .
For instance if you were going to use an ATmel FPGA , you 're most likely going to be using their workbench and the language it uses ( Cant remember off the top of my head which it actually is ) as it contains the best integration with the hardware for development and testing purposes .
It would be silly to try to use the other language with an ATmel FPGA unless you already have a large base of components built in that language to port , which if you already had that base set of components , you would already know the answer to the question you ask.When you get to the point that which language use you actually matters , you 'll be fully aware of it and at that point you 'll actually be able to make a decision .
This is true for just about every programming language on the planet , hardware or software .
The language matters a lot less than most programmers think .
The reality of it is , most programmers suck ass , and the reason they are so loudly voiced about 'their ' language and all its 'greatness ' is because they do n't really know how to program , they just know enough to make their preferred language do something useful .
At the extremes of programming its a little different .
If you 're talking about writing software for a micro controller with no memory management support and/or tiny amounts ( or no ) ram , then using Java would be dumb ( even if you had a VM already ) .
C makes more sense , but with little ram , it may waste too many resources there as well , so you 're going to be using assembly in most cases anyway .
When you 're working on a Mac , Linux or Windows desktop PC however , those sort of limitations simply do n't matter to most apps , so any language will do until you come up with a reason the language wo n't work .
Since you know very little about the languages involved at this point , you probably can not make a educated choice at this time .
Even when you do start running into limitations , its likely going to be the same for both languages or a compiler issue .
For instance , there is no 'reason ' a C # app can not be as fast as an app doing the same thing in assembly though it does happen .
It happens because the compilers used to turn C # into actual executable code that the processor understands in not nearly as effecient at generating machine language as an assembly programmer doing only EXACTLY what it has to do and taking advantages of the way the machine itself works.With Verilog and VHDL its all just gates in the end .
At this stage its practically impossible to determine which one will be more effecient for you to use .
You 're coding style , your abilities , the quirks of the compilers , the ease of use and understanding of the tools all matter far more than anything else .
You 'll see plenty of slashdot posts exclaiming which one is better , but the reality of it is , you wo n't know which one is better for YOU and YOUR PROJECT until you get some experience .
Unless you plane on laying out your entire game plan , what you are building , how you intend to go about it , what hardware you 're using and EVERY other specification about your project , than any advice is just a guess and not even an educated one .
Someone may say 'Use VHDL , it does X , Z , Y , and really is easy to use thanks to feature B' .
Feature B sounds important , so you use VHDL .
Turns out that you never use feature B , and becau</tokentext>
<sentencetext>Then the language is almost irrelevant.
A good developer, software or hardware, can use just about anything thrown at them to accomplish the task, given a reference manual for the language.
FPGAs are just another form of programming and should be treated as such.
(Or you could say that software is just an extension of hardware and should be treated as such, doesn't really matter which way it goes).So, to answer your question.
At this point in time, for you, which one you use depends more on non-technical issues such as what hardware you're going to be using to do the initial development.
If you can find a Verilog compiler but not a VHDL for the hardware you're going to start with then the question answers itself.
For instance if you were going to use an ATmel FPGA, you're most likely going to be using their workbench and the language it uses (Cant remember off the top of my head which it actually is) as it contains the best integration with the hardware for development and testing purposes.
It would be silly to try to use the other language with an ATmel FPGA unless you already have a large base of components built in that language to port, which if you already had that base set of components, you would already know the answer to the question you ask.When you get to the point that which language use you actually matters, you'll be fully aware of it and at that point you'll actually be able to make a decision.
This is true for just about every programming language on the planet, hardware or software.
The language matters a lot less than most programmers think.
The reality of it is, most programmers suck ass, and the reason they are so loudly voiced about 'their' language and all its 'greatness' is because they don't really know how to program, they just know enough to make their preferred language do something useful.
At the extremes of programming its a little different.
If you're talking about writing software for a micro controller with no memory management support and/or tiny amounts ( or no) ram, then using Java would be dumb (even if you had a VM already).
C makes more sense, but with little ram, it may waste too many resources there as well, so you're going to be using assembly in most cases anyway.
When you're working on a Mac, Linux or Windows desktop PC however, those sort of limitations simply don't matter to most apps, so any language will do until you come up with a reason the language won't work.
Since you know very little about the languages involved at this point, you probably can not make a educated choice at this time.
Even when you do start running into limitations, its likely going to be the same for both languages or a compiler issue.
For instance, there is no 'reason' a C# app can not be as fast as an app doing the same thing in assembly though it does happen.
It happens because the compilers used to turn C# into actual executable code that the processor understands in not nearly as effecient at generating machine language as an assembly programmer doing only EXACTLY what it has to do and taking advantages of the way the machine itself works.With Verilog and VHDL its all just gates in the end.
At this stage its practically impossible to determine which one will be more effecient for you to use.
You're coding style, your abilities, the quirks of the compilers, the ease of use and understanding of the tools all matter far more than anything else.
You'll see plenty of slashdot posts exclaiming which one is better, but the reality of it is, you won't know which one is better for YOU and YOUR PROJECT until you get some experience.
Unless you plane on laying out your entire game plan, what you are building, how you intend to go about it, what hardware you're using and EVERY other specification about your project, than any advice is just a guess and not even an educated one.
Someone may say 'Use VHDL, it does X, Z, Y, and really is easy to use thanks to feature B'.
Feature B sounds important, so you use VHDL.
Turns out that you never use feature B, and becau</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28166917</id>
	<title>Re:learn digital design, then learn syntax</title>
	<author>Anonymous</author>
	<datestamp>1243865940000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I totally agree. I'm a student and I like VHDL a lot<nobr> <wbr></nobr>;)...</p><p>What I discovered is that I needed to understand all the underlying concepts before writing one line of VHDL.</p><p>Schematics is horrible, unmaintainable (...). VHDL is strongly typed and helps you to avoid a lot of stupid mistakes...</p></htmltext>
<tokenext>I totally agree .
I 'm a student and I like VHDL a lot ; ) ...What I discovered is that I needed to understand all the underlying concepts before writing one line of VHDL.Schematics is horrible , unmaintainable ( ... ) .
VHDL is strongly typed and helps you to avoid a lot of stupid mistakes.. .</tokentext>
<sentencetext>I totally agree.
I'm a student and I like VHDL a lot ;)...What I discovered is that I needed to understand all the underlying concepts before writing one line of VHDL.Schematics is horrible, unmaintainable (...).
VHDL is strongly typed and helps you to avoid a lot of stupid mistakes...</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160703</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160883</id>
	<title>go verilog</title>
	<author>Khashishi</author>
	<datestamp>1243761840000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>VHDL is powerful but is too general. Basically, you can make the language do whatever you want, (not just limited to gate code, but any sort of modeling or computation, period), but it's a pain in the ass to do it. Pretty much all the operators and symbols (even '1', '0', 'h', etc) need to be defined before you can do anything, making it a feat to actually get work done. Well, there are standard libraries for stuff, but there are issues with multiply defined symbols and stuff in different libraries.</p><p>VHDL is very verbose and requires a lot of boilerplate code to do the simplest tasks. That said, it does scale reasonably well.</p><p>I think Verilog is more specifically geared toward FPGA gate code, and so it's a lot simpler to use. You don't have to fight the language like in VHDL. Go Verilog.</p></htmltext>
<tokenext>VHDL is powerful but is too general .
Basically , you can make the language do whatever you want , ( not just limited to gate code , but any sort of modeling or computation , period ) , but it 's a pain in the ass to do it .
Pretty much all the operators and symbols ( even '1 ' , '0 ' , 'h ' , etc ) need to be defined before you can do anything , making it a feat to actually get work done .
Well , there are standard libraries for stuff , but there are issues with multiply defined symbols and stuff in different libraries.VHDL is very verbose and requires a lot of boilerplate code to do the simplest tasks .
That said , it does scale reasonably well.I think Verilog is more specifically geared toward FPGA gate code , and so it 's a lot simpler to use .
You do n't have to fight the language like in VHDL .
Go Verilog .</tokentext>
<sentencetext>VHDL is powerful but is too general.
Basically, you can make the language do whatever you want, (not just limited to gate code, but any sort of modeling or computation, period), but it's a pain in the ass to do it.
Pretty much all the operators and symbols (even '1', '0', 'h', etc) need to be defined before you can do anything, making it a feat to actually get work done.
Well, there are standard libraries for stuff, but there are issues with multiply defined symbols and stuff in different libraries.VHDL is very verbose and requires a lot of boilerplate code to do the simplest tasks.
That said, it does scale reasonably well.I think Verilog is more specifically geared toward FPGA gate code, and so it's a lot simpler to use.
You don't have to fight the language like in VHDL.
Go Verilog.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161603</id>
	<title>Re:Where are you located?</title>
	<author>reverend schmuley</author>
	<datestamp>1243768140000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext> You mentioned Pong Chu's book 'FPGA Prototyping by Verilog Examples'. He has another book with almost the same title that uses VHDL examples. It is very good for a quick cookbook type of book. He has examples of many basic circuits and modules. The foundation for making your own PONG is outlined, although the full implementation is left for an exercise. He also gets into running the PicoBlaze microcontroller module. I think the books are almost identical, just showing how to make common hardware with the language of your choice. Pong Chu also wrote 'RTL Hardware Design Using VHDL'. This book is very well written and covers general RTL design concepts that are applicable to any language. However, VHDL's RTL synthesis substandard (IEEE 1076.6) is used exclusively for implementation examples.
 Both languages have tradeoffs which are pretty well known. For FPGA based class, you aren't as concerned about behavioral modeling; you want synthesizable code. Just make sure you use books that focus (like Pong Chu's) on the synthesis aspect of whatever language you are using. The fact that VHDL has a synthesis standard seems like a plus in that department but, some people might say that doesn't matter so much.</htmltext>
<tokenext>You mentioned Pong Chu 's book 'FPGA Prototyping by Verilog Examples' .
He has another book with almost the same title that uses VHDL examples .
It is very good for a quick cookbook type of book .
He has examples of many basic circuits and modules .
The foundation for making your own PONG is outlined , although the full implementation is left for an exercise .
He also gets into running the PicoBlaze microcontroller module .
I think the books are almost identical , just showing how to make common hardware with the language of your choice .
Pong Chu also wrote 'RTL Hardware Design Using VHDL' .
This book is very well written and covers general RTL design concepts that are applicable to any language .
However , VHDL 's RTL synthesis substandard ( IEEE 1076.6 ) is used exclusively for implementation examples .
Both languages have tradeoffs which are pretty well known .
For FPGA based class , you are n't as concerned about behavioral modeling ; you want synthesizable code .
Just make sure you use books that focus ( like Pong Chu 's ) on the synthesis aspect of whatever language you are using .
The fact that VHDL has a synthesis standard seems like a plus in that department but , some people might say that does n't matter so much .</tokentext>
<sentencetext> You mentioned Pong Chu's book 'FPGA Prototyping by Verilog Examples'.
He has another book with almost the same title that uses VHDL examples.
It is very good for a quick cookbook type of book.
He has examples of many basic circuits and modules.
The foundation for making your own PONG is outlined, although the full implementation is left for an exercise.
He also gets into running the PicoBlaze microcontroller module.
I think the books are almost identical, just showing how to make common hardware with the language of your choice.
Pong Chu also wrote 'RTL Hardware Design Using VHDL'.
This book is very well written and covers general RTL design concepts that are applicable to any language.
However, VHDL's RTL synthesis substandard (IEEE 1076.6) is used exclusively for implementation examples.
Both languages have tradeoffs which are pretty well known.
For FPGA based class, you aren't as concerned about behavioral modeling; you want synthesizable code.
Just make sure you use books that focus (like Pong Chu's) on the synthesis aspect of whatever language you are using.
The fact that VHDL has a synthesis standard seems like a plus in that department but, some people might say that doesn't matter so much.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161031</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243762920000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext><p>This person has programmed a single board and considers himself knowledgeable?</p><p>1) The syntax is incredibly similar to C.  Which is why it is always described as "C like" to people who have very little experience in HDL.</p><p>2) HDL ARE programming languages.  It compiles and then it runs when its placed in its environment just like EVERY program ever written is supposed to do.</p><p>Thank you for telling us what your reading to better educate yourself.</p><p>@ OP<br>As someone who has spent A LOT of time using both in university, I would say Verilog is the easiest to learn because its syntax is very closely related to C.  VHDL is better if you absolutely must have full control of the resulting performance on the FPGA.  Even then its mostly affected by the performance of the compiler.</p><p>I prefer Verilog but being able to add VHDL on the resume can't hurt your students.  Spend a few weeks on VHDL first then switch to Verilog.  Your students will curse you when they find out how much easier Verilog is, but its better the teach the hard way first before the student becomes dependent on the easy way.</p></htmltext>
<tokenext>This person has programmed a single board and considers himself knowledgeable ? 1 ) The syntax is incredibly similar to C. Which is why it is always described as " C like " to people who have very little experience in HDL.2 ) HDL ARE programming languages .
It compiles and then it runs when its placed in its environment just like EVERY program ever written is supposed to do.Thank you for telling us what your reading to better educate yourself .
@ OPAs someone who has spent A LOT of time using both in university , I would say Verilog is the easiest to learn because its syntax is very closely related to C. VHDL is better if you absolutely must have full control of the resulting performance on the FPGA .
Even then its mostly affected by the performance of the compiler.I prefer Verilog but being able to add VHDL on the resume ca n't hurt your students .
Spend a few weeks on VHDL first then switch to Verilog .
Your students will curse you when they find out how much easier Verilog is , but its better the teach the hard way first before the student becomes dependent on the easy way .</tokentext>
<sentencetext>This person has programmed a single board and considers himself knowledgeable?1) The syntax is incredibly similar to C.  Which is why it is always described as "C like" to people who have very little experience in HDL.2) HDL ARE programming languages.
It compiles and then it runs when its placed in its environment just like EVERY program ever written is supposed to do.Thank you for telling us what your reading to better educate yourself.
@ OPAs someone who has spent A LOT of time using both in university, I would say Verilog is the easiest to learn because its syntax is very closely related to C.  VHDL is better if you absolutely must have full control of the resulting performance on the FPGA.
Even then its mostly affected by the performance of the compiler.I prefer Verilog but being able to add VHDL on the resume can't hurt your students.
Spend a few weeks on VHDL first then switch to Verilog.
Your students will curse you when they find out how much easier Verilog is, but its better the teach the hard way first before the student becomes dependent on the easy way.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28178181</id>
	<title>BASIC?!?!?!?!?!</title>
	<author>Anonymous</author>
	<datestamp>1243883700000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>what about basic... without the "v i s u a l"... that would be a very interesting way to to program FPGAs...
hey, tell you what? go ahead... GOTO not considered harmful anymore... I, GOD, give you permission and my blessing</htmltext>
<tokenext>what about basic... without the " v i s u a l " ... that would be a very interesting way to to program FPGAs.. . hey , tell you what ?
go ahead... GOTO not considered harmful anymore... I , GOD , give you permission and my blessing</tokentext>
<sentencetext>what about basic... without the "v i s u a l"... that would be a very interesting way to to program FPGAs...
hey, tell you what?
go ahead... GOTO not considered harmful anymore... I, GOD, give you permission and my blessing</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28167243</id>
	<title>Your students will always need the other one.</title>
	<author>stephen70edwards</author>
	<datestamp>1243867560000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Both are awful languages from a theoretical standpoint.  Practically, the synthesis subset accepted by RTL tools renders them almost identical, although their spirits are actually quite different. VHDL is more verbose but has the more rigorous type system.  I chose to teach it based more-or-less on a coin flip. Whatever you choose, your students' first employers will be using the other one, so it doesn't really matter.

My class at Columbia can be found at
<a href="http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/" title="columbia.edu" rel="nofollow">http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/</a> [columbia.edu]</htmltext>
<tokenext>Both are awful languages from a theoretical standpoint .
Practically , the synthesis subset accepted by RTL tools renders them almost identical , although their spirits are actually quite different .
VHDL is more verbose but has the more rigorous type system .
I chose to teach it based more-or-less on a coin flip .
Whatever you choose , your students ' first employers will be using the other one , so it does n't really matter .
My class at Columbia can be found at http : //www1.cs.columbia.edu/ ~ sedwards/classes/2009/4840/ [ columbia.edu ]</tokentext>
<sentencetext>Both are awful languages from a theoretical standpoint.
Practically, the synthesis subset accepted by RTL tools renders them almost identical, although their spirits are actually quite different.
VHDL is more verbose but has the more rigorous type system.
I chose to teach it based more-or-less on a coin flip.
Whatever you choose, your students' first employers will be using the other one, so it doesn't really matter.
My class at Columbia can be found at
http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/ [columbia.edu]</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160421</id>
	<title>It doesn't matter</title>
	<author>Anonymous</author>
	<datestamp>1243802100000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>If you understand how to design hardware, either will get the job done.  If you don't, both will give you crap.</p></htmltext>
<tokenext>If you understand how to design hardware , either will get the job done .
If you do n't , both will give you crap .</tokentext>
<sentencetext>If you understand how to design hardware, either will get the job done.
If you don't, both will give you crap.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160725</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243760940000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><blockquote><div><p>In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.</p></div>
</blockquote><p>
I'll second this.  The courses I took in school (Georgia Tech) did everything in VHDL.  Some of those I knew who went on to work in the field remarked that they wished we had learned Verilog instead, as it's much more common in industry.  The impression I always got was that "Verilog vs. VHDL" is somewhat like "C vs. Pascal" used to be - the former is used a lot more in real applications, and allows more "bare metal" access, while the latter is a better teaching/modeling tool, and gets used more in academia.  Which one you choose, then, should probably be based on whether your focus is mainly to train people for jobs in which they'll use a HDL, or teach them the concepts involved.  Sort of like (to make another flawed analogy) IT vs. Computer Science.
</p></div>
	</htmltext>
<tokenext>In industry , as far as I can tell , Verilog seems to be more used in North America and VHDL in Europe , so that might affect what you care about , too .
I 'll second this .
The courses I took in school ( Georgia Tech ) did everything in VHDL .
Some of those I knew who went on to work in the field remarked that they wished we had learned Verilog instead , as it 's much more common in industry .
The impression I always got was that " Verilog vs. VHDL " is somewhat like " C vs. Pascal " used to be - the former is used a lot more in real applications , and allows more " bare metal " access , while the latter is a better teaching/modeling tool , and gets used more in academia .
Which one you choose , then , should probably be based on whether your focus is mainly to train people for jobs in which they 'll use a HDL , or teach them the concepts involved .
Sort of like ( to make another flawed analogy ) IT vs. Computer Science .</tokentext>
<sentencetext>In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.
I'll second this.
The courses I took in school (Georgia Tech) did everything in VHDL.
Some of those I knew who went on to work in the field remarked that they wished we had learned Verilog instead, as it's much more common in industry.
The impression I always got was that "Verilog vs. VHDL" is somewhat like "C vs. Pascal" used to be - the former is used a lot more in real applications, and allows more "bare metal" access, while the latter is a better teaching/modeling tool, and gets used more in academia.
Which one you choose, then, should probably be based on whether your focus is mainly to train people for jobs in which they'll use a HDL, or teach them the concepts involved.
Sort of like (to make another flawed analogy) IT vs. Computer Science.

	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162127</id>
	<title>I like VHDL...  Here are some cool reasons why.</title>
	<author>Xilinx\_guy</author>
	<datestamp>1243773060000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext>Disclaimer #1:   I work for Xilinx.   Disclaimer #2:  I used to teach VHDL, back in the late 90's.    I too, voted on the IEEE effort for standardization on the synthesizable subset for VHDL, and boy what a waste of time that was.  But I digress.   Here are some cool reasons why VHDL is better than Verilog.    1.  Recursion.  You can write recursive hardware components that instantiate smaller versions of themselves.    Recursion is cool, but tools hate it.   The Xilinx tools complain about it, but will still produce the right hardware.   Recursion can be used for Multipliers, adder trees, priority encoders, muxes, and just about anything where divide and conquer actually works.   2.  Attributes.  VHDL attributes translate straight to EDIF properties, and let you do cool stuff like physical design in an FPGA,  EDIF properties in the netlist let you do anything from selecting the power-on state of a flop, to setting the logic function of a lookup table (LUT), or setting the initial value of a RAM.  Even better, you can pass LOC (Location) or RLOC (relative location) properties, allowing you to physically place the location of a component in the target device.  You can even specify directed routing constraints that lock down the signal path to a specific defined route.   Verilog will sort of let you do this, but only in a pragma (code comment).  Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL, but not in Verilog.    3.  Compile time elaboration of constants.   This sounds incredibly obscure, but is actually very powerful.  During elaboration, constants are evaluated.  Constants can be defined by an arbitrarily complex function call.    These functions can perform arbitrary computation, as well as read and write files.   A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM.   I use compile time function calls to do precomputation on stuff where I don't know the generic parameters in advance.   An example of this would be a state machine to detect a serial unique word, with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter.   Or how about CRC's?   You see people writing C programs to generate Verilog designs to calculate a CRC, but in VHDL, you can compute the parity matrices directly at compile time given a static CRC as a generic parameter.  Once the parity matrix is generated, it's easy to generate the hardware to calculate it.   It's a bit trickier to do error correction with a CRC, but also possible.   These calculations are hideously difficult in Verilog.   4.  Type REAL.   VHDL has a floating data type REAL, and even a IEEE library REALMATH to use it with (Sine, Cosine, Tangent, etc).  You can do very nice geometry calculations during elaboration with this library.   Or, for the EE's, you can do stuff like generate coefficents for a raised root cosine filter in VHDL.   Now REAL types can't be synthesized directly, since they have no direct hardware representation.. but REAL can be converted to INTEGERs, and integers can be turned in to real hardware with a precision of up to 32 bits.  That's plenty in most cases in an FPGA.
<p>
Now having said all that...  System Verilog has a LOT going for it, and when the tools catch up to the Language Reference Manual, then it could be an extremely powerful design language.   This  presentation from DATE 2004 shows why. <a href="http://www.systemverilog.org/techpapers/date04\_systemverilog.pdf" title="systemverilog.org" rel="nofollow">http://www.systemverilog.org/techpapers/date04\_systemverilog.pdf</a> [systemverilog.org]</p></htmltext>
<tokenext>Disclaimer # 1 : I work for Xilinx .
Disclaimer # 2 : I used to teach VHDL , back in the late 90 's .
I too , voted on the IEEE effort for standardization on the synthesizable subset for VHDL , and boy what a waste of time that was .
But I digress .
Here are some cool reasons why VHDL is better than Verilog .
1. Recursion .
You can write recursive hardware components that instantiate smaller versions of themselves .
Recursion is cool , but tools hate it .
The Xilinx tools complain about it , but will still produce the right hardware .
Recursion can be used for Multipliers , adder trees , priority encoders , muxes , and just about anything where divide and conquer actually works .
2. Attributes .
VHDL attributes translate straight to EDIF properties , and let you do cool stuff like physical design in an FPGA , EDIF properties in the netlist let you do anything from selecting the power-on state of a flop , to setting the logic function of a lookup table ( LUT ) , or setting the initial value of a RAM .
Even better , you can pass LOC ( Location ) or RLOC ( relative location ) properties , allowing you to physically place the location of a component in the target device .
You can even specify directed routing constraints that lock down the signal path to a specific defined route .
Verilog will sort of let you do this , but only in a pragma ( code comment ) .
Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL , but not in Verilog .
3. Compile time elaboration of constants .
This sounds incredibly obscure , but is actually very powerful .
During elaboration , constants are evaluated .
Constants can be defined by an arbitrarily complex function call .
These functions can perform arbitrary computation , as well as read and write files .
A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM .
I use compile time function calls to do precomputation on stuff where I do n't know the generic parameters in advance .
An example of this would be a state machine to detect a serial unique word , with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter .
Or how about CRC 's ?
You see people writing C programs to generate Verilog designs to calculate a CRC , but in VHDL , you can compute the parity matrices directly at compile time given a static CRC as a generic parameter .
Once the parity matrix is generated , it 's easy to generate the hardware to calculate it .
It 's a bit trickier to do error correction with a CRC , but also possible .
These calculations are hideously difficult in Verilog .
4. Type REAL .
VHDL has a floating data type REAL , and even a IEEE library REALMATH to use it with ( Sine , Cosine , Tangent , etc ) .
You can do very nice geometry calculations during elaboration with this library .
Or , for the EE 's , you can do stuff like generate coefficents for a raised root cosine filter in VHDL .
Now REAL types ca n't be synthesized directly , since they have no direct hardware representation.. but REAL can be converted to INTEGERs , and integers can be turned in to real hardware with a precision of up to 32 bits .
That 's plenty in most cases in an FPGA .
Now having said all that... System Verilog has a LOT going for it , and when the tools catch up to the Language Reference Manual , then it could be an extremely powerful design language .
This presentation from DATE 2004 shows why .
http : //www.systemverilog.org/techpapers/date04 \ _systemverilog.pdf [ systemverilog.org ]</tokentext>
<sentencetext>Disclaimer #1:   I work for Xilinx.
Disclaimer #2:  I used to teach VHDL, back in the late 90's.
I too, voted on the IEEE effort for standardization on the synthesizable subset for VHDL, and boy what a waste of time that was.
But I digress.
Here are some cool reasons why VHDL is better than Verilog.
1.  Recursion.
You can write recursive hardware components that instantiate smaller versions of themselves.
Recursion is cool, but tools hate it.
The Xilinx tools complain about it, but will still produce the right hardware.
Recursion can be used for Multipliers, adder trees, priority encoders, muxes, and just about anything where divide and conquer actually works.
2.  Attributes.
VHDL attributes translate straight to EDIF properties, and let you do cool stuff like physical design in an FPGA,  EDIF properties in the netlist let you do anything from selecting the power-on state of a flop, to setting the logic function of a lookup table (LUT), or setting the initial value of a RAM.
Even better, you can pass LOC (Location) or RLOC (relative location) properties, allowing you to physically place the location of a component in the target device.
You can even specify directed routing constraints that lock down the signal path to a specific defined route.
Verilog will sort of let you do this, but only in a pragma (code comment).
Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL, but not in Verilog.
3.  Compile time elaboration of constants.
This sounds incredibly obscure, but is actually very powerful.
During elaboration, constants are evaluated.
Constants can be defined by an arbitrarily complex function call.
These functions can perform arbitrary computation, as well as read and write files.
A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM.
I use compile time function calls to do precomputation on stuff where I don't know the generic parameters in advance.
An example of this would be a state machine to detect a serial unique word, with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter.
Or how about CRC's?
You see people writing C programs to generate Verilog designs to calculate a CRC, but in VHDL, you can compute the parity matrices directly at compile time given a static CRC as a generic parameter.
Once the parity matrix is generated, it's easy to generate the hardware to calculate it.
It's a bit trickier to do error correction with a CRC, but also possible.
These calculations are hideously difficult in Verilog.
4.  Type REAL.
VHDL has a floating data type REAL, and even a IEEE library REALMATH to use it with (Sine, Cosine, Tangent, etc).
You can do very nice geometry calculations during elaboration with this library.
Or, for the EE's, you can do stuff like generate coefficents for a raised root cosine filter in VHDL.
Now REAL types can't be synthesized directly, since they have no direct hardware representation.. but REAL can be converted to INTEGERs, and integers can be turned in to real hardware with a precision of up to 32 bits.
That's plenty in most cases in an FPGA.
Now having said all that...  System Verilog has a LOT going for it, and when the tools catch up to the Language Reference Manual, then it could be an extremely powerful design language.
This  presentation from DATE 2004 shows why.
http://www.systemverilog.org/techpapers/date04\_systemverilog.pdf [systemverilog.org]</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28168419</id>
	<title>MyHDL</title>
	<author>jandecaluwe</author>
	<datestamp>1243872600000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Why not consider a HDL for the google generation<nobr> <wbr></nobr>:-)</p><p>
&nbsp; &nbsp; &nbsp; &nbsp; <a href="http://www.myhdl.org/doku.php" title="myhdl.org" rel="nofollow">http://www.myhdl.org/doku.php</a> [myhdl.org]</p><p>This is Python used as a HDL - conversion to Verilog and VHDL included!</p><p>Jan</p></htmltext>
<tokenext>Why not consider a HDL for the google generation : - )         http : //www.myhdl.org/doku.php [ myhdl.org ] This is Python used as a HDL - conversion to Verilog and VHDL included ! Jan</tokentext>
<sentencetext>Why not consider a HDL for the google generation :-)
        http://www.myhdl.org/doku.php [myhdl.org]This is Python used as a HDL - conversion to Verilog and VHDL included!Jan</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28168619</id>
	<title>VHDL for teaching</title>
	<author>ReplicantSD1</author>
	<datestamp>1243873500000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Verilog gives you enough rope to easily hang yourself.
VHDL gives you so little rope you'll want to hang yourself.
As a vehicle for teaching H/W design though, I think VHDL would be better. It's much more explicit and rules oriented, and looks like you're describing H/W. Once you've learned VHDL, picking up Verilog is fairly trivial. I would think going in the other direction would be a bit harder.

Language Bias Disclaimer: I've been using VHDL for 10 years, and Verilog for 2...</htmltext>
<tokenext>Verilog gives you enough rope to easily hang yourself .
VHDL gives you so little rope you 'll want to hang yourself .
As a vehicle for teaching H/W design though , I think VHDL would be better .
It 's much more explicit and rules oriented , and looks like you 're describing H/W .
Once you 've learned VHDL , picking up Verilog is fairly trivial .
I would think going in the other direction would be a bit harder .
Language Bias Disclaimer : I 've been using VHDL for 10 years , and Verilog for 2.. .</tokentext>
<sentencetext>Verilog gives you enough rope to easily hang yourself.
VHDL gives you so little rope you'll want to hang yourself.
As a vehicle for teaching H/W design though, I think VHDL would be better.
It's much more explicit and rules oriented, and looks like you're describing H/W.
Once you've learned VHDL, picking up Verilog is fairly trivial.
I would think going in the other direction would be a bit harder.
Language Bias Disclaimer: I've been using VHDL for 10 years, and Verilog for 2...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160715</id>
	<title>This is not CS</title>
	<author>Sybert42</author>
	<datestamp>1243760880000</datestamp>
	<modclass>None</modclass>
	<modscore>-1</modscore>
	<htmltext><p>/. is mainly CS.</p></htmltext>
<tokenext>/ .
is mainly CS .</tokentext>
<sentencetext>/.
is mainly CS.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162469</id>
	<title>VHDL</title>
	<author>Anonymous</author>
	<datestamp>1243775880000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I like VHDL better. Sure the learning curve is steeper in terms of syntax but due to its different syntax students won't be as easily tricked into thinking that things are going to execute sequentially.</p></htmltext>
<tokenext>I like VHDL better .
Sure the learning curve is steeper in terms of syntax but due to its different syntax students wo n't be as easily tricked into thinking that things are going to execute sequentially .</tokentext>
<sentencetext>I like VHDL better.
Sure the learning curve is steeper in terms of syntax but due to its different syntax students won't be as easily tricked into thinking that things are going to execute sequentially.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161563</id>
	<title>Re:Verilog 100\% No Question</title>
	<author>negro\_monolito</author>
	<datestamp>1243767900000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Before going any further, I will admit my bias and say that I did teach a class (lab actually) where the final project was to write a two player pong game on an FPGA. I am sorry if you felt that was a waste of your time when you did it (I am assuming that is where your anger is coming from).</p><p>That said, saying that no one should ever use FPGAs/CPLDs is pure non-sense. Every engineering problem can be solved multiple ways, and outright excluding FPGAs as a valid method is unwise at best. It's like saying that no one should ever use microcontrollers because full blown desktops have more power anyways.</p><p>Do you know how microprocessors are designed? Have you made a MIPS or (gasp) even your own processor? I'll give you a hint, they're not made with a bag of NAND TTLs and wire-wrap. They are designed in VHDL, Verilog, or some other proprietary HDL language, simulated, verified, etc. and fabricated. Sure the first microprocessor was built with individual gates, but that's not how it is done now. Similarly, they aren't made with Java on a JVM.</p><p>And yes, I have used both VHDL and Verilog. VHDL is cumbersome with its long admittedly convoluted syntax when you come from a software perspective, and Verilog seems easier because superficially it is "C-like". But they both "make sense and flow" just fine from the perspective of an EE. The reason for-loops and whiles don't exist (*) in because at the hardware level, they don't exist. When someone writes a for-loop in C/Java/(other high level language) it is compiled/assembled into machine code for a microprocessor. The microprocessor itself executes this code with flip/flops and logic gates, that's it. No loops or even logic statements because there is no such equivalent in the hardware world.</p><p>Also, as for FPGA/CPLDs not providing a competitive performance to investment ratio (the execution speed up to engineer implementation time), that is also not true. As soon as you take a problem from a procedural domain to a concurrent domain, it is often possible to do more work in a given amount of time. It's partly the same reason why we are seeing Intel/AMD move from increased clock frequencies to increased processing cores (power issues aside). And when you concede that using a concurrent domain is sometimes more useful and decide to create an ASIC in your product, well guess what? If you already designed it on an FPGA you are 90\% there (or 99\% if you believe the Xilinx/Altera kool-aid).</p><p>So to conclude, I wouldn't design a GUI with HDL and I wouldn't design an H.264 cellphone decoder chip in C/Java. I would use the best tool for the job.</p><p>* Yes, I know that VHDL for loops are similar to C-macros, and wait statements will work in simulation like a while loop, but neither will work how a C programmer expects them to.</p></htmltext>
<tokenext>Before going any further , I will admit my bias and say that I did teach a class ( lab actually ) where the final project was to write a two player pong game on an FPGA .
I am sorry if you felt that was a waste of your time when you did it ( I am assuming that is where your anger is coming from ) .That said , saying that no one should ever use FPGAs/CPLDs is pure non-sense .
Every engineering problem can be solved multiple ways , and outright excluding FPGAs as a valid method is unwise at best .
It 's like saying that no one should ever use microcontrollers because full blown desktops have more power anyways.Do you know how microprocessors are designed ?
Have you made a MIPS or ( gasp ) even your own processor ?
I 'll give you a hint , they 're not made with a bag of NAND TTLs and wire-wrap .
They are designed in VHDL , Verilog , or some other proprietary HDL language , simulated , verified , etc .
and fabricated .
Sure the first microprocessor was built with individual gates , but that 's not how it is done now .
Similarly , they are n't made with Java on a JVM.And yes , I have used both VHDL and Verilog .
VHDL is cumbersome with its long admittedly convoluted syntax when you come from a software perspective , and Verilog seems easier because superficially it is " C-like " .
But they both " make sense and flow " just fine from the perspective of an EE .
The reason for-loops and whiles do n't exist ( * ) in because at the hardware level , they do n't exist .
When someone writes a for-loop in C/Java/ ( other high level language ) it is compiled/assembled into machine code for a microprocessor .
The microprocessor itself executes this code with flip/flops and logic gates , that 's it .
No loops or even logic statements because there is no such equivalent in the hardware world.Also , as for FPGA/CPLDs not providing a competitive performance to investment ratio ( the execution speed up to engineer implementation time ) , that is also not true .
As soon as you take a problem from a procedural domain to a concurrent domain , it is often possible to do more work in a given amount of time .
It 's partly the same reason why we are seeing Intel/AMD move from increased clock frequencies to increased processing cores ( power issues aside ) .
And when you concede that using a concurrent domain is sometimes more useful and decide to create an ASIC in your product , well guess what ?
If you already designed it on an FPGA you are 90 \ % there ( or 99 \ % if you believe the Xilinx/Altera kool-aid ) .So to conclude , I would n't design a GUI with HDL and I would n't design an H.264 cellphone decoder chip in C/Java .
I would use the best tool for the job .
* Yes , I know that VHDL for loops are similar to C-macros , and wait statements will work in simulation like a while loop , but neither will work how a C programmer expects them to .</tokentext>
<sentencetext>Before going any further, I will admit my bias and say that I did teach a class (lab actually) where the final project was to write a two player pong game on an FPGA.
I am sorry if you felt that was a waste of your time when you did it (I am assuming that is where your anger is coming from).That said, saying that no one should ever use FPGAs/CPLDs is pure non-sense.
Every engineering problem can be solved multiple ways, and outright excluding FPGAs as a valid method is unwise at best.
It's like saying that no one should ever use microcontrollers because full blown desktops have more power anyways.Do you know how microprocessors are designed?
Have you made a MIPS or (gasp) even your own processor?
I'll give you a hint, they're not made with a bag of NAND TTLs and wire-wrap.
They are designed in VHDL, Verilog, or some other proprietary HDL language, simulated, verified, etc.
and fabricated.
Sure the first microprocessor was built with individual gates, but that's not how it is done now.
Similarly, they aren't made with Java on a JVM.And yes, I have used both VHDL and Verilog.
VHDL is cumbersome with its long admittedly convoluted syntax when you come from a software perspective, and Verilog seems easier because superficially it is "C-like".
But they both "make sense and flow" just fine from the perspective of an EE.
The reason for-loops and whiles don't exist (*) in because at the hardware level, they don't exist.
When someone writes a for-loop in C/Java/(other high level language) it is compiled/assembled into machine code for a microprocessor.
The microprocessor itself executes this code with flip/flops and logic gates, that's it.
No loops or even logic statements because there is no such equivalent in the hardware world.Also, as for FPGA/CPLDs not providing a competitive performance to investment ratio (the execution speed up to engineer implementation time), that is also not true.
As soon as you take a problem from a procedural domain to a concurrent domain, it is often possible to do more work in a given amount of time.
It's partly the same reason why we are seeing Intel/AMD move from increased clock frequencies to increased processing cores (power issues aside).
And when you concede that using a concurrent domain is sometimes more useful and decide to create an ASIC in your product, well guess what?
If you already designed it on an FPGA you are 90\% there (or 99\% if you believe the Xilinx/Altera kool-aid).So to conclude, I wouldn't design a GUI with HDL and I wouldn't design an H.264 cellphone decoder chip in C/Java.
I would use the best tool for the job.
* Yes, I know that VHDL for loops are similar to C-macros, and wait statements will work in simulation like a while loop, but neither will work how a C programmer expects them to.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160811</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28164341</id>
	<title>Verilog but don't use Xilinx ISE&#226;&#166;</title>
	<author>Anonymous</author>
	<datestamp>1243792020000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>1</modscore>
	<htmltext><p>This post is remarkably well timed: I'm currently procrastinating over doing an assignment in Verilog for an undergrad course in FPGAs.</p><p>I'd definitely pick Verilog.  The main problem will be what you choose for compiling.  If you use ISE 9.2 (the immediately obvious choice for a Spartan board), make sure you check your brake lines every time you get in the car&#226;"your students will hate you.</p><p>I think Verilog offers the best combination of usability and actually learning about hardware.</p></htmltext>
<tokenext>This post is remarkably well timed : I 'm currently procrastinating over doing an assignment in Verilog for an undergrad course in FPGAs.I 'd definitely pick Verilog .
The main problem will be what you choose for compiling .
If you use ISE 9.2 ( the immediately obvious choice for a Spartan board ) , make sure you check your brake lines every time you get in the car   " your students will hate you.I think Verilog offers the best combination of usability and actually learning about hardware .</tokentext>
<sentencetext>This post is remarkably well timed: I'm currently procrastinating over doing an assignment in Verilog for an undergrad course in FPGAs.I'd definitely pick Verilog.
The main problem will be what you choose for compiling.
If you use ISE 9.2 (the immediately obvious choice for a Spartan board), make sure you check your brake lines every time you get in the carâ"your students will hate you.I think Verilog offers the best combination of usability and actually learning about hardware.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28164583</id>
	<title>Verilog Of course...</title>
	<author>tanveer1979</author>
	<datestamp>1243794660000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><tt>I work in the EDA field now, and first 4 years of my career were spent in Design Verification.<br><br>Based on what I see, VHDL is mostly on its way out. Most new innovations in design tools center around verilog. Due it its being more "free" as opposed to the super strict VHDL, its gaining popularity in the last bastions of VHDL, the european universities.<br>Nowadays all big design companies use Verilog almost exclusively, with only legacy blocks in VHDL.<br><br>So Verilog is the way to go, and also easier to learn. However beware, if you come from a software background, you will have difficulty adjusting to the "time" concept of logic programming languages. So brush up the design basics first, how to blocking/non-blocking statements work, and how does an "event" driven language work.<br></tt></htmltext>
<tokenext>I work in the EDA field now , and first 4 years of my career were spent in Design Verification.Based on what I see , VHDL is mostly on its way out .
Most new innovations in design tools center around verilog .
Due it its being more " free " as opposed to the super strict VHDL , its gaining popularity in the last bastions of VHDL , the european universities.Nowadays all big design companies use Verilog almost exclusively , with only legacy blocks in VHDL.So Verilog is the way to go , and also easier to learn .
However beware , if you come from a software background , you will have difficulty adjusting to the " time " concept of logic programming languages .
So brush up the design basics first , how to blocking/non-blocking statements work , and how does an " event " driven language work .</tokentext>
<sentencetext>I work in the EDA field now, and first 4 years of my career were spent in Design Verification.Based on what I see, VHDL is mostly on its way out.
Most new innovations in design tools center around verilog.
Due it its being more "free" as opposed to the super strict VHDL, its gaining popularity in the last bastions of VHDL, the european universities.Nowadays all big design companies use Verilog almost exclusively, with only legacy blocks in VHDL.So Verilog is the way to go, and also easier to learn.
However beware, if you come from a software background, you will have difficulty adjusting to the "time" concept of logic programming languages.
So brush up the design basics first, how to blocking/non-blocking statements work, and how does an "event" driven language work.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161027</id>
	<title>Simulink</title>
	<author>giampy</author>
	<datestamp>1243762920000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>The industry seem to be leaning toward higher-level languages like MATLAB/Simulink, which let you generate automatically VHDL code for your FPGAs from an higher level functional schematic diagram. So you might want to include them perhaps towards the second part the course.</p></htmltext>
<tokenext>The industry seem to be leaning toward higher-level languages like MATLAB/Simulink , which let you generate automatically VHDL code for your FPGAs from an higher level functional schematic diagram .
So you might want to include them perhaps towards the second part the course .</tokentext>
<sentencetext>The industry seem to be leaning toward higher-level languages like MATLAB/Simulink, which let you generate automatically VHDL code for your FPGAs from an higher level functional schematic diagram.
So you might want to include them perhaps towards the second part the course.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162411</id>
	<title>A vote for VHDL</title>
	<author>Anonymous</author>
	<datestamp>1243775400000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>1</modscore>
	<htmltext><p>Disclaimer: I've been using VHDL design &amp; verification for ~10 years (but also Verilog, and Specman E, PSL, etc.) &amp; I'm a bit of language geek</p><p>VHDL is more verbose, but more capable than Verilog. There are several points that in my opinion make VHDL a better language for teaching (and for design and simulation):<br>1. It's *MUCH* harder to shoot yourself in the foot than with Verilog. VHDL is strongly typed (which is partly why it's more verbose) and generally when you write code you're not going to run into weird problems. Verilog is a minefield by comparison. Even very simple code can have race conditions &amp; may synthesize differently from how it simulates. When I took a Verilog course many years ago, the first thing they handed us was fridge magnet with 7 rules (do/do not). If you don't follow those you risk shooting yourself in the foot. Nothing like that is required of VHDL.<br>2. VHDL is a lot better for simulation than Verilog. Partly because of Verilog's problems, once you step away from the RTL design subset you run the risk of spending hours debugging stupid things that a VHDL compiler would've caught, or that wouldn't happen in VHDL. With VHDL you can write very sophisticated testbenches(1). As an example I've written some constrained random + coverage testbenches in the style of Specman (or SystemVerilog). Try doing that with plain Verilog.<br>3. Verilog is a very simple language. It's harder to write reusable code. It's much easier to create parameterized, scalable, reusable blocks in VHDL through the use of generics and generate statements, multi-dimensional arrays, etc.. In fact this is my default style in VHDL. If it can be parameterized it should be. This applies especially to FPGA designs where the design requirements are typically more fluid than in ASIC designs. Also making designs parametric forces you to think more deeply about what you're implementing and to get to the core of an idea which in my opinion leads to cleaner, more maintainable code (again IMO a big deal for FPGA designs)</p><p>Having said all that:<br>1) VHDL seems to be on the wane a bit and the bastard child of Verilog, a.k.a System Verilog seems to be everyone's favorite language. There are definitely benefits to System Verilog. It's a much better language than Verilog. The problem is that it is based \_on\_ Verilog and shares many of the problems.<br>2) As has been mentioned above a good designer should be able to pick up a new language quickly, especially the design subset and a seasoned designer should at least be able to read both languages. You \_will\_ run into both of them in your work even if your shop primarily uses one.<br>3) It's true that ASIC designers tend to use Verilog, while FPGA designers seem to favor VHDL</p><p>(1) BTW the reality is that if you're doing your job as a designer right, you spend *way* more time writing testbenches than writing synthesizable RTL</p></htmltext>
<tokenext>Disclaimer : I 've been using VHDL design &amp; verification for ~ 10 years ( but also Verilog , and Specman E , PSL , etc .
) &amp; I 'm a bit of language geekVHDL is more verbose , but more capable than Verilog .
There are several points that in my opinion make VHDL a better language for teaching ( and for design and simulation ) : 1 .
It 's * MUCH * harder to shoot yourself in the foot than with Verilog .
VHDL is strongly typed ( which is partly why it 's more verbose ) and generally when you write code you 're not going to run into weird problems .
Verilog is a minefield by comparison .
Even very simple code can have race conditions &amp; may synthesize differently from how it simulates .
When I took a Verilog course many years ago , the first thing they handed us was fridge magnet with 7 rules ( do/do not ) .
If you do n't follow those you risk shooting yourself in the foot .
Nothing like that is required of VHDL.2 .
VHDL is a lot better for simulation than Verilog .
Partly because of Verilog 's problems , once you step away from the RTL design subset you run the risk of spending hours debugging stupid things that a VHDL compiler would 've caught , or that would n't happen in VHDL .
With VHDL you can write very sophisticated testbenches ( 1 ) .
As an example I 've written some constrained random + coverage testbenches in the style of Specman ( or SystemVerilog ) .
Try doing that with plain Verilog.3 .
Verilog is a very simple language .
It 's harder to write reusable code .
It 's much easier to create parameterized , scalable , reusable blocks in VHDL through the use of generics and generate statements , multi-dimensional arrays , etc.. In fact this is my default style in VHDL .
If it can be parameterized it should be .
This applies especially to FPGA designs where the design requirements are typically more fluid than in ASIC designs .
Also making designs parametric forces you to think more deeply about what you 're implementing and to get to the core of an idea which in my opinion leads to cleaner , more maintainable code ( again IMO a big deal for FPGA designs ) Having said all that : 1 ) VHDL seems to be on the wane a bit and the bastard child of Verilog , a.k.a System Verilog seems to be everyone 's favorite language .
There are definitely benefits to System Verilog .
It 's a much better language than Verilog .
The problem is that it is based \ _on \ _ Verilog and shares many of the problems.2 ) As has been mentioned above a good designer should be able to pick up a new language quickly , especially the design subset and a seasoned designer should at least be able to read both languages .
You \ _will \ _ run into both of them in your work even if your shop primarily uses one.3 ) It 's true that ASIC designers tend to use Verilog , while FPGA designers seem to favor VHDL ( 1 ) BTW the reality is that if you 're doing your job as a designer right , you spend * way * more time writing testbenches than writing synthesizable RTL</tokentext>
<sentencetext>Disclaimer: I've been using VHDL design &amp; verification for ~10 years (but also Verilog, and Specman E, PSL, etc.
) &amp; I'm a bit of language geekVHDL is more verbose, but more capable than Verilog.
There are several points that in my opinion make VHDL a better language for teaching (and for design and simulation):1.
It's *MUCH* harder to shoot yourself in the foot than with Verilog.
VHDL is strongly typed (which is partly why it's more verbose) and generally when you write code you're not going to run into weird problems.
Verilog is a minefield by comparison.
Even very simple code can have race conditions &amp; may synthesize differently from how it simulates.
When I took a Verilog course many years ago, the first thing they handed us was fridge magnet with 7 rules (do/do not).
If you don't follow those you risk shooting yourself in the foot.
Nothing like that is required of VHDL.2.
VHDL is a lot better for simulation than Verilog.
Partly because of Verilog's problems, once you step away from the RTL design subset you run the risk of spending hours debugging stupid things that a VHDL compiler would've caught, or that wouldn't happen in VHDL.
With VHDL you can write very sophisticated testbenches(1).
As an example I've written some constrained random + coverage testbenches in the style of Specman (or SystemVerilog).
Try doing that with plain Verilog.3.
Verilog is a very simple language.
It's harder to write reusable code.
It's much easier to create parameterized, scalable, reusable blocks in VHDL through the use of generics and generate statements, multi-dimensional arrays, etc.. In fact this is my default style in VHDL.
If it can be parameterized it should be.
This applies especially to FPGA designs where the design requirements are typically more fluid than in ASIC designs.
Also making designs parametric forces you to think more deeply about what you're implementing and to get to the core of an idea which in my opinion leads to cleaner, more maintainable code (again IMO a big deal for FPGA designs)Having said all that:1) VHDL seems to be on the wane a bit and the bastard child of Verilog, a.k.a System Verilog seems to be everyone's favorite language.
There are definitely benefits to System Verilog.
It's a much better language than Verilog.
The problem is that it is based \_on\_ Verilog and shares many of the problems.2) As has been mentioned above a good designer should be able to pick up a new language quickly, especially the design subset and a seasoned designer should at least be able to read both languages.
You \_will\_ run into both of them in your work even if your shop primarily uses one.3) It's true that ASIC designers tend to use Verilog, while FPGA designers seem to favor VHDL(1) BTW the reality is that if you're doing your job as a designer right, you spend *way* more time writing testbenches than writing synthesizable RTL</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165063</id>
	<title>Proper spelling of "holy war"</title>
	<author>Anonymous</author>
	<datestamp>1243887600000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>"undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?"</p><p>The first step for an undergrad student, before even attempting to learn anything complex like VHDL/Verilog would be to learn proper spelling of "holy war" in IT-related domains.<br>Read my lips, it is spelled : "Vi vs. Emacs".<br>Now insigthful people can understand you<nobr> <wbr></nobr>:-)</p></htmltext>
<tokenext>" undecidable holy-war question along the lines of ATI/nVidia , AMD/Intel , Coke/Pepsi , etc... ?
" The first step for an undergrad student , before even attempting to learn anything complex like VHDL/Verilog would be to learn proper spelling of " holy war " in IT-related domains.Read my lips , it is spelled : " Vi vs. Emacs " .Now insigthful people can understand you : - )</tokentext>
<sentencetext>"undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?
"The first step for an undergrad student, before even attempting to learn anything complex like VHDL/Verilog would be to learn proper spelling of "holy war" in IT-related domains.Read my lips, it is spelled : "Vi vs. Emacs".Now insigthful people can understand you :-)</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28178799</id>
	<title>Re:FPGA SDK's for Student's to work on...</title>
	<author>Man On Pink Corner</author>
	<datestamp>1243975980000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I'd pony up the extra few bucks for the Nexys2 instead of the Basys.  The USB implementation is better documented, and there's a nice Hirose connector.</p></htmltext>
<tokenext>I 'd pony up the extra few bucks for the Nexys2 instead of the Basys .
The USB implementation is better documented , and there 's a nice Hirose connector .</tokentext>
<sentencetext>I'd pony up the extra few bucks for the Nexys2 instead of the Basys.
The USB implementation is better documented, and there's a nice Hirose connector.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161007</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160943</id>
	<title>Test Benches</title>
	<author>Anonymous</author>
	<datestamp>1243762260000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>  I strongly disagree with the idea that these aren't programming languages and that all you need to know about is the synthesizable subset of each language.</p><p>
&nbsp; &nbsp; I've worked for several years using VHDL for ASIC/FPGA work.  Invariably, I spent 2-3 times as long working on the simulation / test-bench as I did on the VHDL that was actually synthesized into the product.  There are a lot of very interesting language features that you can exploit to make the testing more flexible and easy.  If you tried to make a simulation test-bench out of the synthesizable subset, you're being a lot less efficient than you could be.</p><p>
&nbsp; Also, I have a strong preference for VHDL's strong typing and pseudo-object oriented features over the wild-west down-in-the-bits Verilog style.  I think it's easier to manage complexity and reuse code in VHDL.</p><p>That said, Verilog is definitely more popular in the US, which is important to consider if you're looking for marketable skills.  If, on the other hand, you find yourself in a position to choose the language once you already have a job, I'd strongly recommend VHDL</p></htmltext>
<tokenext>I strongly disagree with the idea that these are n't programming languages and that all you need to know about is the synthesizable subset of each language .
    I 've worked for several years using VHDL for ASIC/FPGA work .
Invariably , I spent 2-3 times as long working on the simulation / test-bench as I did on the VHDL that was actually synthesized into the product .
There are a lot of very interesting language features that you can exploit to make the testing more flexible and easy .
If you tried to make a simulation test-bench out of the synthesizable subset , you 're being a lot less efficient than you could be .
  Also , I have a strong preference for VHDL 's strong typing and pseudo-object oriented features over the wild-west down-in-the-bits Verilog style .
I think it 's easier to manage complexity and reuse code in VHDL.That said , Verilog is definitely more popular in the US , which is important to consider if you 're looking for marketable skills .
If , on the other hand , you find yourself in a position to choose the language once you already have a job , I 'd strongly recommend VHDL</tokentext>
<sentencetext>  I strongly disagree with the idea that these aren't programming languages and that all you need to know about is the synthesizable subset of each language.
    I've worked for several years using VHDL for ASIC/FPGA work.
Invariably, I spent 2-3 times as long working on the simulation / test-bench as I did on the VHDL that was actually synthesized into the product.
There are a lot of very interesting language features that you can exploit to make the testing more flexible and easy.
If you tried to make a simulation test-bench out of the synthesizable subset, you're being a lot less efficient than you could be.
  Also, I have a strong preference for VHDL's strong typing and pseudo-object oriented features over the wild-west down-in-the-bits Verilog style.
I think it's easier to manage complexity and reuse code in VHDL.That said, Verilog is definitely more popular in the US, which is important to consider if you're looking for marketable skills.
If, on the other hand, you find yourself in a position to choose the language once you already have a job, I'd strongly recommend VHDL</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161049</id>
	<title>Verilog is more concise</title>
	<author>OutputLogic</author>
	<datestamp>1243763100000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Verilog is more concise.
Example: 16-bit LFSR counter in Verilog has 24 lines of code. The same in VHDL is 41.

(I generated the LFSR counter using OutputLogic.com online tools)</htmltext>
<tokenext>Verilog is more concise .
Example : 16-bit LFSR counter in Verilog has 24 lines of code .
The same in VHDL is 41 .
( I generated the LFSR counter using OutputLogic.com online tools )</tokentext>
<sentencetext>Verilog is more concise.
Example: 16-bit LFSR counter in Verilog has 24 lines of code.
The same in VHDL is 41.
(I generated the LFSR counter using OutputLogic.com online tools)</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162401</id>
	<title>Verilog....</title>
	<author>emh203</author>
	<datestamp>1243775340000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>If your target is synthesis for an FPGA I would go with Verilog.

Here is the bottom line:    Any synthesis function you could do in VHDL could always be done in Verilog with fewer lines of code and will look alot simpler.

VHDL is very verbose.


If you search the internet there was a neat article about a Verilog vs. VHDL "competition" where one had to synthesize a logic function (targeting real hardware) in a fixed period of time.

Of the people that finished,  those using verilog were able to yield results that could run at higher clock speeds with fewer lines of code.</htmltext>
<tokenext>If your target is synthesis for an FPGA I would go with Verilog .
Here is the bottom line : Any synthesis function you could do in VHDL could always be done in Verilog with fewer lines of code and will look alot simpler .
VHDL is very verbose .
If you search the internet there was a neat article about a Verilog vs. VHDL " competition " where one had to synthesize a logic function ( targeting real hardware ) in a fixed period of time .
Of the people that finished , those using verilog were able to yield results that could run at higher clock speeds with fewer lines of code .</tokentext>
<sentencetext>If your target is synthesis for an FPGA I would go with Verilog.
Here is the bottom line:    Any synthesis function you could do in VHDL could always be done in Verilog with fewer lines of code and will look alot simpler.
VHDL is very verbose.
If you search the internet there was a neat article about a Verilog vs. VHDL "competition" where one had to synthesize a logic function (targeting real hardware) in a fixed period of time.
Of the people that finished,  those using verilog were able to yield results that could run at higher clock speeds with fewer lines of code.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160881</id>
	<title>Verilog is the future</title>
	<author>Anonymous</author>
	<datestamp>1243761840000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>VHDL is the best bet if you are doing professional FPGA design, especially in the gov't/mil/aero/space industries.  There is a lot of legacy code in VHDL and you're more likely to buy IP cores in VHDL.  It is quite wordy, but the strong typing saves debugging time.</p><p>But for hobby or commercial use, Verilog is the clear winner.  Verilog has much better FOSS tools (I never could get isim or freehdl to work right, and I do this for a living).  The openHPSDR firmware is all in Verilog.  The weak typing makes Verilog easier to learn, and it's more compact.  System Verilog is a fantastic advancement and offers much that VHDL doesn't.  I suspect everyone will be writing their testbenches in system verilog (or perhaps SystemC), even if the synthesizable code is in VHDL.  Might as well learn just one language and do everything in Verilog.</p><p>Schematic capture will limit you; it's fine for small-time hacking but if you really want to learn this stuff you can't beat an HDL.  Also be careful about graphical tools like LabView, CoreFire, Simulink, etc for FPGA design.  You'll end up only understanding that one proprietary design entry language and won't be able to share designs and knowledge with the broader world.</p></htmltext>
<tokenext>VHDL is the best bet if you are doing professional FPGA design , especially in the gov't/mil/aero/space industries .
There is a lot of legacy code in VHDL and you 're more likely to buy IP cores in VHDL .
It is quite wordy , but the strong typing saves debugging time.But for hobby or commercial use , Verilog is the clear winner .
Verilog has much better FOSS tools ( I never could get isim or freehdl to work right , and I do this for a living ) .
The openHPSDR firmware is all in Verilog .
The weak typing makes Verilog easier to learn , and it 's more compact .
System Verilog is a fantastic advancement and offers much that VHDL does n't .
I suspect everyone will be writing their testbenches in system verilog ( or perhaps SystemC ) , even if the synthesizable code is in VHDL .
Might as well learn just one language and do everything in Verilog.Schematic capture will limit you ; it 's fine for small-time hacking but if you really want to learn this stuff you ca n't beat an HDL .
Also be careful about graphical tools like LabView , CoreFire , Simulink , etc for FPGA design .
You 'll end up only understanding that one proprietary design entry language and wo n't be able to share designs and knowledge with the broader world .</tokentext>
<sentencetext>VHDL is the best bet if you are doing professional FPGA design, especially in the gov't/mil/aero/space industries.
There is a lot of legacy code in VHDL and you're more likely to buy IP cores in VHDL.
It is quite wordy, but the strong typing saves debugging time.But for hobby or commercial use, Verilog is the clear winner.
Verilog has much better FOSS tools (I never could get isim or freehdl to work right, and I do this for a living).
The openHPSDR firmware is all in Verilog.
The weak typing makes Verilog easier to learn, and it's more compact.
System Verilog is a fantastic advancement and offers much that VHDL doesn't.
I suspect everyone will be writing their testbenches in system verilog (or perhaps SystemC), even if the synthesizable code is in VHDL.
Might as well learn just one language and do everything in Verilog.Schematic capture will limit you; it's fine for small-time hacking but if you really want to learn this stuff you can't beat an HDL.
Also be careful about graphical tools like LabView, CoreFire, Simulink, etc for FPGA design.
You'll end up only understanding that one proprietary design entry language and won't be able to share designs and knowledge with the broader world.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161993</id>
	<title>Re:Where are you located?</title>
	<author>Darinbob</author>
	<datestamp>1243771740000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext>I've not programmed in HDLs but I've read some of their programming.  All the companies I've been at has used VHDL, though very often the main developers will gripe that they'd rather be using Verilog...<br><br>I'd agree with the assessment that if this is for students, then always teach the more rigorous language first.  This goes for programming languages too.  If you teach what is popular today, you end up with graduates who have difficulty adapting in the future.  VHDL is the more rigorous and formal language, which is precisely what it needed with hardware design.</htmltext>
<tokenext>I 've not programmed in HDLs but I 've read some of their programming .
All the companies I 've been at has used VHDL , though very often the main developers will gripe that they 'd rather be using Verilog...I 'd agree with the assessment that if this is for students , then always teach the more rigorous language first .
This goes for programming languages too .
If you teach what is popular today , you end up with graduates who have difficulty adapting in the future .
VHDL is the more rigorous and formal language , which is precisely what it needed with hardware design .</tokentext>
<sentencetext>I've not programmed in HDLs but I've read some of their programming.
All the companies I've been at has used VHDL, though very often the main developers will gripe that they'd rather be using Verilog...I'd agree with the assessment that if this is for students, then always teach the more rigorous language first.
This goes for programming languages too.
If you teach what is popular today, you end up with graduates who have difficulty adapting in the future.
VHDL is the more rigorous and formal language, which is precisely what it needed with hardware design.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160761</id>
	<title>System Verilog</title>
	<author>alain94040</author>
	<datestamp>1243761120000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>If your goal is to prevent the students from ever completing their project and running on real hardware, then pick VHDL. Its ADA-like compiler will reject every possible attempt at coding until you master the language.</p><p>At least with Verilog you'll compile some gates, which may or may not work functionally, but at least you'll have fun discovering what your code does in hardware.</p><p>I was part of the IEEE committee which standardized the VHDL subset for synthesis (a fiasco, but that's another story).</p><p>10 years ago, the debate between Verilog and VHDL was that the US was using Verilog and academia and Europe were using VHDL. That's over: pretty much everyone switched to some form of SystemVerilog.</p><p>In the end, what really matters is that students can go back and forth between any given language construct (blocking assignment, missing assignment, for loop, etc.) and its hardware equivalent (flip-fop, latch, mux, etc.).</p><p>Very few people are good at this. The ones that do make $150,000+ in Silicon Valley. So it is definitely a good career path.</p></htmltext>
<tokenext>If your goal is to prevent the students from ever completing their project and running on real hardware , then pick VHDL .
Its ADA-like compiler will reject every possible attempt at coding until you master the language.At least with Verilog you 'll compile some gates , which may or may not work functionally , but at least you 'll have fun discovering what your code does in hardware.I was part of the IEEE committee which standardized the VHDL subset for synthesis ( a fiasco , but that 's another story ) .10 years ago , the debate between Verilog and VHDL was that the US was using Verilog and academia and Europe were using VHDL .
That 's over : pretty much everyone switched to some form of SystemVerilog.In the end , what really matters is that students can go back and forth between any given language construct ( blocking assignment , missing assignment , for loop , etc .
) and its hardware equivalent ( flip-fop , latch , mux , etc .
) .Very few people are good at this .
The ones that do make $ 150,000 + in Silicon Valley .
So it is definitely a good career path .</tokentext>
<sentencetext>If your goal is to prevent the students from ever completing their project and running on real hardware, then pick VHDL.
Its ADA-like compiler will reject every possible attempt at coding until you master the language.At least with Verilog you'll compile some gates, which may or may not work functionally, but at least you'll have fun discovering what your code does in hardware.I was part of the IEEE committee which standardized the VHDL subset for synthesis (a fiasco, but that's another story).10 years ago, the debate between Verilog and VHDL was that the US was using Verilog and academia and Europe were using VHDL.
That's over: pretty much everyone switched to some form of SystemVerilog.In the end, what really matters is that students can go back and forth between any given language construct (blocking assignment, missing assignment, for loop, etc.
) and its hardware equivalent (flip-fop, latch, mux, etc.
).Very few people are good at this.
The ones that do make $150,000+ in Silicon Valley.
So it is definitely a good career path.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160611</id>
	<title>Re:Where are you located?</title>
	<author>jcasper</author>
	<datestamp>1243803360000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>The quote I've always heard (not sure where it came from):  "VHDL was created by hardware engineers who know nothing about programming languages.  Verilog was created by computer scientists who know nothing about hardware."<br>
<br>
In practice I've had to deal with both on a regular basis, including single designs with both VHDL and Verilog modules. I'd say teach digital design and let them learn whatever language they want to implement what they learn in class; Xilinx tools can handle both seamlessly, why not let them choose?  Show examples from both in the slides.</div>
	</htmltext>
<tokenext>The quote I 've always heard ( not sure where it came from ) : " VHDL was created by hardware engineers who know nothing about programming languages .
Verilog was created by computer scientists who know nothing about hardware .
" In practice I 've had to deal with both on a regular basis , including single designs with both VHDL and Verilog modules .
I 'd say teach digital design and let them learn whatever language they want to implement what they learn in class ; Xilinx tools can handle both seamlessly , why not let them choose ?
Show examples from both in the slides .</tokentext>
<sentencetext>The quote I've always heard (not sure where it came from):  "VHDL was created by hardware engineers who know nothing about programming languages.
Verilog was created by computer scientists who know nothing about hardware.
"

In practice I've had to deal with both on a regular basis, including single designs with both VHDL and Verilog modules.
I'd say teach digital design and let them learn whatever language they want to implement what they learn in class; Xilinx tools can handle both seamlessly, why not let them choose?
Show examples from both in the slides.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161129</id>
	<title>Verilog</title>
	<author>bear24rw</author>
	<datestamp>1243763940000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Last quarter i took digital design at university of cincinnati and we used verilog, i found it much easier to understand than VHDL. I would say go with verilog if you are just starting out.</htmltext>
<tokenext>Last quarter i took digital design at university of cincinnati and we used verilog , i found it much easier to understand than VHDL .
I would say go with verilog if you are just starting out .</tokentext>
<sentencetext>Last quarter i took digital design at university of cincinnati and we used verilog, i found it much easier to understand than VHDL.
I would say go with verilog if you are just starting out.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28185947</id>
	<title>Maybe I can help</title>
	<author>AltiumMan</author>
	<datestamp>1243972320000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I used to lecture in all this sort of stuff and I now work for Altium creating training videos.

If your course is on \_using\_ FPGAs then I'd encourage you to not stop at the VHDL/Verilog languages.  You're going to have to ask yourself if you are creating a HDL programming language course or a 'Designing with FPGAs' course.

There are a number of higher level FPGA design systems out there that can raise abstraction above the HDL and will allow you to build FPGA systems much faster than you could with an HDL alone. Take a look at what Altium (www.altium.com) offers in terms of software AND hardware - they have a vendor neutral FPGA development platform that allows you to plug in different FPGAs (from different vendors) along with a whole heap of peripheral boards.

I'm happy to talk you through it all if you have any questions.
Marty</htmltext>
<tokenext>I used to lecture in all this sort of stuff and I now work for Altium creating training videos .
If your course is on \ _using \ _ FPGAs then I 'd encourage you to not stop at the VHDL/Verilog languages .
You 're going to have to ask yourself if you are creating a HDL programming language course or a 'Designing with FPGAs ' course .
There are a number of higher level FPGA design systems out there that can raise abstraction above the HDL and will allow you to build FPGA systems much faster than you could with an HDL alone .
Take a look at what Altium ( www.altium.com ) offers in terms of software AND hardware - they have a vendor neutral FPGA development platform that allows you to plug in different FPGAs ( from different vendors ) along with a whole heap of peripheral boards .
I 'm happy to talk you through it all if you have any questions .
Marty</tokentext>
<sentencetext>I used to lecture in all this sort of stuff and I now work for Altium creating training videos.
If your course is on \_using\_ FPGAs then I'd encourage you to not stop at the VHDL/Verilog languages.
You're going to have to ask yourself if you are creating a HDL programming language course or a 'Designing with FPGAs' course.
There are a number of higher level FPGA design systems out there that can raise abstraction above the HDL and will allow you to build FPGA systems much faster than you could with an HDL alone.
Take a look at what Altium (www.altium.com) offers in terms of software AND hardware - they have a vendor neutral FPGA development platform that allows you to plug in different FPGAs (from different vendors) along with a whole heap of peripheral boards.
I'm happy to talk you through it all if you have any questions.
Marty</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160775</id>
	<title>Re:Something completely different...</title>
	<author>Anonymous</author>
	<datestamp>1243761180000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>1</modscore>
	<htmltext><p>But 1000 lines of VHDL makes for a really, really tiny design, far smaller than anything implemented in a modern FPGA in a modern product.  If you're still using schematic capture, you must still be developing for CPLD-sized devices.</p></htmltext>
<tokenext>But 1000 lines of VHDL makes for a really , really tiny design , far smaller than anything implemented in a modern FPGA in a modern product .
If you 're still using schematic capture , you must still be developing for CPLD-sized devices .</tokentext>
<sentencetext>But 1000 lines of VHDL makes for a really, really tiny design, far smaller than anything implemented in a modern FPGA in a modern product.
If you're still using schematic capture, you must still be developing for CPLD-sized devices.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160411</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28167655</id>
	<title>Start with verilog and graduate to VHDL</title>
	<author>coolNsunny</author>
	<datestamp>1243869360000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>First the quick answer - for what you need to do/achieve, Verilog sounds like the right choice. Focussing on digital design basics and synthesis is, IMO, far more important and crucial for beginners than worrying about language constructs. Although I wouldn't take that arguement too far and advocate that schematic entry is an acceptable choice instead of RTL. VHDL or Verolog will not teach you digital design. Just like C/C++ will not teach you computer architecture. VHDL vs Verilog choice becomes more important when the project's size (people) and complexity grows. For large and complex projects VHDL offers far more powerful constructs like generic programming (unconstrained ports) and abstraction (multiple entity-architecture, configuration etc) and the verbosity/cumbersomeness of the language is easily offset by the benefits. I have been an avid VHDL user for over 10 years. For sufficiently complex projects I have been able to convince and convert verilog users to adopt VHDL except for my current project where some people still use schematic entry - SIGH.</htmltext>
<tokenext>First the quick answer - for what you need to do/achieve , Verilog sounds like the right choice .
Focussing on digital design basics and synthesis is , IMO , far more important and crucial for beginners than worrying about language constructs .
Although I would n't take that arguement too far and advocate that schematic entry is an acceptable choice instead of RTL .
VHDL or Verolog will not teach you digital design .
Just like C/C + + will not teach you computer architecture .
VHDL vs Verilog choice becomes more important when the project 's size ( people ) and complexity grows .
For large and complex projects VHDL offers far more powerful constructs like generic programming ( unconstrained ports ) and abstraction ( multiple entity-architecture , configuration etc ) and the verbosity/cumbersomeness of the language is easily offset by the benefits .
I have been an avid VHDL user for over 10 years .
For sufficiently complex projects I have been able to convince and convert verilog users to adopt VHDL except for my current project where some people still use schematic entry - SIGH .</tokentext>
<sentencetext>First the quick answer - for what you need to do/achieve, Verilog sounds like the right choice.
Focussing on digital design basics and synthesis is, IMO, far more important and crucial for beginners than worrying about language constructs.
Although I wouldn't take that arguement too far and advocate that schematic entry is an acceptable choice instead of RTL.
VHDL or Verolog will not teach you digital design.
Just like C/C++ will not teach you computer architecture.
VHDL vs Verilog choice becomes more important when the project's size (people) and complexity grows.
For large and complex projects VHDL offers far more powerful constructs like generic programming (unconstrained ports) and abstraction (multiple entity-architecture, configuration etc) and the verbosity/cumbersomeness of the language is easily offset by the benefits.
I have been an avid VHDL user for over 10 years.
For sufficiently complex projects I have been able to convince and convert verilog users to adopt VHDL except for my current project where some people still use schematic entry - SIGH.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160919</id>
	<title>Personally I'd go for verilog</title>
	<author>petermgreen</author>
	<datestamp>1243762080000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>VHDL has an incrediablly anal-retentive type system and has some silly ideas like the splitting of entities and architectures. It's also old meaning you need a lot of boilerplate to manually import  STD\_LOGIC stuff (which is what the synthisis tool vendors tell you to use for everything)</p><p>Whichever you use be aware that both VHDL and Verilog weredesigned as hardware simulation languages not hardware synthisis languages. This means it is vital to get to know the synthisis tool you will be using. It is vital to know what warnings matter and what can be safely ignored and which are important, what parts of the language must be avoided, how to assign clocks to clock nets, how to use the timing analyser (without timing alalysis you don't know if your code will actually work) and so on if you are going to use the languages for FPGA programming.</p></htmltext>
<tokenext>VHDL has an incrediablly anal-retentive type system and has some silly ideas like the splitting of entities and architectures .
It 's also old meaning you need a lot of boilerplate to manually import STD \ _LOGIC stuff ( which is what the synthisis tool vendors tell you to use for everything ) Whichever you use be aware that both VHDL and Verilog weredesigned as hardware simulation languages not hardware synthisis languages .
This means it is vital to get to know the synthisis tool you will be using .
It is vital to know what warnings matter and what can be safely ignored and which are important , what parts of the language must be avoided , how to assign clocks to clock nets , how to use the timing analyser ( without timing alalysis you do n't know if your code will actually work ) and so on if you are going to use the languages for FPGA programming .</tokentext>
<sentencetext>VHDL has an incrediablly anal-retentive type system and has some silly ideas like the splitting of entities and architectures.
It's also old meaning you need a lot of boilerplate to manually import  STD\_LOGIC stuff (which is what the synthisis tool vendors tell you to use for everything)Whichever you use be aware that both VHDL and Verilog weredesigned as hardware simulation languages not hardware synthisis languages.
This means it is vital to get to know the synthisis tool you will be using.
It is vital to know what warnings matter and what can be safely ignored and which are important, what parts of the language must be avoided, how to assign clocks to clock nets, how to use the timing analyser (without timing alalysis you don't know if your code will actually work) and so on if you are going to use the languages for FPGA programming.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165577</id>
	<title>Depends</title>
	<author>Anonymous</author>
	<datestamp>1243852680000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>If you're planning to work in Europe, learn VHDL. If in USA, Verilog. Of course it's not bad to know both of them.</htmltext>
<tokenext>If you 're planning to work in Europe , learn VHDL .
If in USA , Verilog .
Of course it 's not bad to know both of them .</tokentext>
<sentencetext>If you're planning to work in Europe, learn VHDL.
If in USA, Verilog.
Of course it's not bad to know both of them.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28169493</id>
	<title>LabVIEW FPGA module</title>
	<author>Anonymous</author>
	<datestamp>1243877220000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I've used LabVIEW FPGA module to develop FPGAs before. I found it to be rather intuitive, but compile times were very slow. I've never used Verilog or VHDL though so I can't compare.</p><p>LabVIEW's FPGA module uses a graphical programming language named G, so you see what goes on visually.</p></htmltext>
<tokenext>I 've used LabVIEW FPGA module to develop FPGAs before .
I found it to be rather intuitive , but compile times were very slow .
I 've never used Verilog or VHDL though so I ca n't compare.LabVIEW 's FPGA module uses a graphical programming language named G , so you see what goes on visually .</tokentext>
<sentencetext>I've used LabVIEW FPGA module to develop FPGAs before.
I found it to be rather intuitive, but compile times were very slow.
I've never used Verilog or VHDL though so I can't compare.LabVIEW's FPGA module uses a graphical programming language named G, so you see what goes on visually.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28166713</id>
	<title>Re:Where are you located?</title>
	<author>bwcbwc</author>
	<datestamp>1243864800000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Why not think of Verilog as a programming language? It has to be the right one though. For example, compare it to Prolog. When you describe the hardware in VHDL or Verilog you are essentially describing the logical rules embodied in the hardware, rather than the process that the logic actually represents. Prolog is a lot closer to this model than a procedural or OO language like C or C++. The key is to step away from a flow-control process model to a set-based logic model mapping inputs to outputs. That doesn't mean you aren't programming, just that you're modelling your program using a different paradigm.</p></htmltext>
<tokenext>Why not think of Verilog as a programming language ?
It has to be the right one though .
For example , compare it to Prolog .
When you describe the hardware in VHDL or Verilog you are essentially describing the logical rules embodied in the hardware , rather than the process that the logic actually represents .
Prolog is a lot closer to this model than a procedural or OO language like C or C + + .
The key is to step away from a flow-control process model to a set-based logic model mapping inputs to outputs .
That does n't mean you are n't programming , just that you 're modelling your program using a different paradigm .</tokentext>
<sentencetext>Why not think of Verilog as a programming language?
It has to be the right one though.
For example, compare it to Prolog.
When you describe the hardware in VHDL or Verilog you are essentially describing the logical rules embodied in the hardware, rather than the process that the logic actually represents.
Prolog is a lot closer to this model than a procedural or OO language like C or C++.
The key is to step away from a flow-control process model to a set-based logic model mapping inputs to outputs.
That doesn't mean you aren't programming, just that you're modelling your program using a different paradigm.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160377</id>
	<title>Re:Where are you located?</title>
	<author>kestasjk</author>
	<datestamp>1243801860000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I had a brief experience with Xilinx during a computer science course. It was (no exaggeration) the most buggy, error/crash-prone Windows 95 throwback nightmare piece of software I've ever used. Everyone in the labs were often unable to complete (simple hardware fundamentals 101) assignments, just because of software problems.<br> <br>

YMMV of course, but if I never have to use Xilinx again I'll be glad.</htmltext>
<tokenext>I had a brief experience with Xilinx during a computer science course .
It was ( no exaggeration ) the most buggy , error/crash-prone Windows 95 throwback nightmare piece of software I 've ever used .
Everyone in the labs were often unable to complete ( simple hardware fundamentals 101 ) assignments , just because of software problems .
YMMV of course , but if I never have to use Xilinx again I 'll be glad .</tokentext>
<sentencetext>I had a brief experience with Xilinx during a computer science course.
It was (no exaggeration) the most buggy, error/crash-prone Windows 95 throwback nightmare piece of software I've ever used.
Everyone in the labs were often unable to complete (simple hardware fundamentals 101) assignments, just because of software problems.
YMMV of course, but if I never have to use Xilinx again I'll be glad.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162517</id>
	<title>Consider Xilinx System Generator</title>
	<author>OutaControl</author>
	<datestamp>1243776300000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext>I've found that I can substantially reduce VHDL development time using <a href="http://www.xilinx.com/tools/sysgen.htm" title="xilinx.com" rel="nofollow"> Xilinx System Generator </a> [xilinx.com] and its toolbox for <a href="http://www.mathworks.com/products/simulink/" title="mathworks.com" rel="nofollow"> Matlab's Simulink </a> [mathworks.com].  Writing VHDL graphically makes understanding and testing substantially easier (for me, at least). <br>
<br>
It has hand-coded VHDL equivalents for each Simulink function.  Generate testbenches, hardware in the loop, etc.  You can merge it directly with your own code by writing a simple high level wrapper.  It interfaces easily with Chipscope as well (generates files to label each of your inputs).</htmltext>
<tokenext>I 've found that I can substantially reduce VHDL development time using Xilinx System Generator [ xilinx.com ] and its toolbox for Matlab 's Simulink [ mathworks.com ] .
Writing VHDL graphically makes understanding and testing substantially easier ( for me , at least ) .
It has hand-coded VHDL equivalents for each Simulink function .
Generate testbenches , hardware in the loop , etc .
You can merge it directly with your own code by writing a simple high level wrapper .
It interfaces easily with Chipscope as well ( generates files to label each of your inputs ) .</tokentext>
<sentencetext>I've found that I can substantially reduce VHDL development time using  Xilinx System Generator  [xilinx.com] and its toolbox for  Matlab's Simulink  [mathworks.com].
Writing VHDL graphically makes understanding and testing substantially easier (for me, at least).
It has hand-coded VHDL equivalents for each Simulink function.
Generate testbenches, hardware in the loop, etc.
You can merge it directly with your own code by writing a simple high level wrapper.
It interfaces easily with Chipscope as well (generates files to label each of your inputs).</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161295</id>
	<title>Verilog is a programming language</title>
	<author>OutputLogic</author>
	<datestamp>1243765680000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Verilog is a programming language that describes hardware. You can program complex algorithms, protocol stacks, even simple operating systems. I've done it during my 9 years working with Verilog.

<br>
<br>
 - outputlogic
<br> <br>
Visit <a href="http://outputlogic.com/" title="outputlogic.com" rel="nofollow">outputlogic.com</a> [outputlogic.com] : tools that improve productivity</htmltext>
<tokenext>Verilog is a programming language that describes hardware .
You can program complex algorithms , protocol stacks , even simple operating systems .
I 've done it during my 9 years working with Verilog .
- outputlogic Visit outputlogic.com [ outputlogic.com ] : tools that improve productivity</tokentext>
<sentencetext>Verilog is a programming language that describes hardware.
You can program complex algorithms, protocol stacks, even simple operating systems.
I've done it during my 9 years working with Verilog.
- outputlogic
 
Visit outputlogic.com [outputlogic.com] : tools that improve productivity</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161271</id>
	<title>Preferences</title>
	<author>StormReaver</author>
	<datestamp>1243765440000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>My first preference would be to have the course taught by someone with real experience with the subject.  If it's going to be the blind leading the blind, it's better to not have the course at all.</p></htmltext>
<tokenext>My first preference would be to have the course taught by someone with real experience with the subject .
If it 's going to be the blind leading the blind , it 's better to not have the course at all .</tokentext>
<sentencetext>My first preference would be to have the course taught by someone with real experience with the subject.
If it's going to be the blind leading the blind, it's better to not have the course at all.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28166283</id>
	<title>I vote Verilog</title>
	<author>happy\_place</author>
	<datestamp>1243861620000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Fwiw, I vote verilog. There's a lot of legacy work done in VHDL, especially in government projects, but pretty much all new development is/has been/etc moving to Verilog, and with System Verilog being open source a lot of your verification tasks are even easier now. If you get a chance to use VCS, you can use C code and verilog together flawlessly. Verilog's rtl level grammar is easier to understand if you're at all familiar with programming concepts, and reads very much like C. Xilinx support for Verilog used to be pretty weak, but nowadays is on par with vhdl. I've worked with both, and find verilog easier to read because of the way that modules and interfaces can all be in a single file, where vhdl always had pieces more spread out, less contained modularly (though that might've been an implementation choice by vendors, dunno).</htmltext>
<tokenext>Fwiw , I vote verilog .
There 's a lot of legacy work done in VHDL , especially in government projects , but pretty much all new development is/has been/etc moving to Verilog , and with System Verilog being open source a lot of your verification tasks are even easier now .
If you get a chance to use VCS , you can use C code and verilog together flawlessly .
Verilog 's rtl level grammar is easier to understand if you 're at all familiar with programming concepts , and reads very much like C. Xilinx support for Verilog used to be pretty weak , but nowadays is on par with vhdl .
I 've worked with both , and find verilog easier to read because of the way that modules and interfaces can all be in a single file , where vhdl always had pieces more spread out , less contained modularly ( though that might 've been an implementation choice by vendors , dunno ) .</tokentext>
<sentencetext>Fwiw, I vote verilog.
There's a lot of legacy work done in VHDL, especially in government projects, but pretty much all new development is/has been/etc moving to Verilog, and with System Verilog being open source a lot of your verification tasks are even easier now.
If you get a chance to use VCS, you can use C code and verilog together flawlessly.
Verilog's rtl level grammar is easier to understand if you're at all familiar with programming concepts, and reads very much like C. Xilinx support for Verilog used to be pretty weak, but nowadays is on par with vhdl.
I've worked with both, and find verilog easier to read because of the way that modules and interfaces can all be in a single file, where vhdl always had pieces more spread out, less contained modularly (though that might've been an implementation choice by vendors, dunno).</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161401</id>
	<title>VIM</title>
	<author>nog\_lorp</author>
	<datestamp>1243766580000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>VIM</p></htmltext>
<tokenext>VIM</tokentext>
<sentencetext>VIM</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161015</id>
	<title>You could try something easier</title>
	<author>Anonymous</author>
	<datestamp>1243762860000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Like http://www.myhdl.org/doku.php. It's basically Python and can be translated to either VHDL or Verilog.</p></htmltext>
<tokenext>Like http : //www.myhdl.org/doku.php .
It 's basically Python and can be translated to either VHDL or Verilog .</tokentext>
<sentencetext>Like http://www.myhdl.org/doku.php.
It's basically Python and can be translated to either VHDL or Verilog.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</id>
	<title>Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243797900000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>5</modscore>
	<htmltext><p>Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.</p><p>In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.</p><p>Personally, I prefer Verilog.</p></htmltext>
<tokenext>Personally , I would say that Verilog is more C-like : weakly typed , compact , efficient notation , whereas VHDL is much more Ada-like : strongly typed , often verbose , but can catch errors that the other one ca n't.In industry , as far as I can tell , Verilog seems to be more used in North America and VHDL in Europe , so that might affect what you care about , too.Personally , I prefer Verilog .</tokentext>
<sentencetext>Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.Personally, I prefer Verilog.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28164765</id>
	<title>verilog (from former designer and instructor)</title>
	<author>Anonymous</author>
	<datestamp>1243796820000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I used to do asic/fpga design in verilog and vhdl for a number of years as a consultant, then I taught digital design at university for 5 years, using both languages. As a number of the previous posts mentioned, it's vital to teach your students to think of hardware while writing the code. The language doesn't really matter,  since you can easily learn the other if you need to. But I found that the students were able to do more sophisticated designs when taught verilog, as opposed to vhdl. I think that's because vhdl has a steeper learning curve - it's verbose and very picky. Verilog has a hidden learning curve because your compiler won't complain about some vital errors, as other posters have pointed out. Just stick with one language so that the students don't get confused.</p><p>It's really important that you master your hdl, do lots of practice designs, because you'll helping your students do lots of debugging in the lab. In the lab, I tell my students that they have to show me a working simulation (i.e. testbench) and a successful synthesis check, before I will look at their hardware for evaluation or debugging. I tell them that they should have a correctly working simulation before trying to download to the board. Unfortunately, they usually don't listen and have trouble debugging their designs. Sadly, I've seem this practice too often in industry as well. I give zero marks for simulation, they have to show me working hardware. FYI, my students spend about 20-30 hours per week working on their designs, outside of scheduled lab/class time.</p><p>Be sure to teach them about synchronous design, we get lots of strange attempts at funny clocking schemes (e.g. capturing input data) and inappropriate uses of resets. Keep changing your design projects every year, or else they'll just copy. Good luck with the course, it'll be a lot of work, but fun.</p></htmltext>
<tokenext>I used to do asic/fpga design in verilog and vhdl for a number of years as a consultant , then I taught digital design at university for 5 years , using both languages .
As a number of the previous posts mentioned , it 's vital to teach your students to think of hardware while writing the code .
The language does n't really matter , since you can easily learn the other if you need to .
But I found that the students were able to do more sophisticated designs when taught verilog , as opposed to vhdl .
I think that 's because vhdl has a steeper learning curve - it 's verbose and very picky .
Verilog has a hidden learning curve because your compiler wo n't complain about some vital errors , as other posters have pointed out .
Just stick with one language so that the students do n't get confused.It 's really important that you master your hdl , do lots of practice designs , because you 'll helping your students do lots of debugging in the lab .
In the lab , I tell my students that they have to show me a working simulation ( i.e .
testbench ) and a successful synthesis check , before I will look at their hardware for evaluation or debugging .
I tell them that they should have a correctly working simulation before trying to download to the board .
Unfortunately , they usually do n't listen and have trouble debugging their designs .
Sadly , I 've seem this practice too often in industry as well .
I give zero marks for simulation , they have to show me working hardware .
FYI , my students spend about 20-30 hours per week working on their designs , outside of scheduled lab/class time.Be sure to teach them about synchronous design , we get lots of strange attempts at funny clocking schemes ( e.g .
capturing input data ) and inappropriate uses of resets .
Keep changing your design projects every year , or else they 'll just copy .
Good luck with the course , it 'll be a lot of work , but fun .</tokentext>
<sentencetext>I used to do asic/fpga design in verilog and vhdl for a number of years as a consultant, then I taught digital design at university for 5 years, using both languages.
As a number of the previous posts mentioned, it's vital to teach your students to think of hardware while writing the code.
The language doesn't really matter,  since you can easily learn the other if you need to.
But I found that the students were able to do more sophisticated designs when taught verilog, as opposed to vhdl.
I think that's because vhdl has a steeper learning curve - it's verbose and very picky.
Verilog has a hidden learning curve because your compiler won't complain about some vital errors, as other posters have pointed out.
Just stick with one language so that the students don't get confused.It's really important that you master your hdl, do lots of practice designs, because you'll helping your students do lots of debugging in the lab.
In the lab, I tell my students that they have to show me a working simulation (i.e.
testbench) and a successful synthesis check, before I will look at their hardware for evaluation or debugging.
I tell them that they should have a correctly working simulation before trying to download to the board.
Unfortunately, they usually don't listen and have trouble debugging their designs.
Sadly, I've seem this practice too often in industry as well.
I give zero marks for simulation, they have to show me working hardware.
FYI, my students spend about 20-30 hours per week working on their designs, outside of scheduled lab/class time.Be sure to teach them about synchronous design, we get lots of strange attempts at funny clocking schemes (e.g.
capturing input data) and inappropriate uses of resets.
Keep changing your design projects every year, or else they'll just copy.
Good luck with the course, it'll be a lot of work, but fun.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28168849</id>
	<title>Re:Where are you located?</title>
	<author>RunsWithMatches</author>
	<datestamp>1243874640000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I've been a designer of hardware using FPGAs since 1990, which is close to the beginning FPGAs.  In that time, about nineteen years as I add it up, I've rarely done a board that didn't have several of both major varieties,  Xilinx and Altera. I can say confidently and without fear of contradiction, that the worst software between the two is the one you're currently working with.</htmltext>
<tokenext>I 've been a designer of hardware using FPGAs since 1990 , which is close to the beginning FPGAs .
In that time , about nineteen years as I add it up , I 've rarely done a board that did n't have several of both major varieties , Xilinx and Altera .
I can say confidently and without fear of contradiction , that the worst software between the two is the one you 're currently working with .</tokentext>
<sentencetext>I've been a designer of hardware using FPGAs since 1990, which is close to the beginning FPGAs.
In that time, about nineteen years as I add it up, I've rarely done a board that didn't have several of both major varieties,  Xilinx and Altera.
I can say confidently and without fear of contradiction, that the worst software between the two is the one you're currently working with.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160377</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160573</id>
	<title>C-to-Verilog dot com</title>
	<author>Anonymous</author>
	<datestamp>1243803180000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Hi,</p><p>Another possible solution is to use automated translation between C to VHDL or Verilog.   The website http://www.c-to-verilog.com is an open source project which gives you a compiler and an on-line service for compiling C to Verilog.</p></htmltext>
<tokenext>Hi,Another possible solution is to use automated translation between C to VHDL or Verilog .
The website http : //www.c-to-verilog.com is an open source project which gives you a compiler and an on-line service for compiling C to Verilog .</tokentext>
<sentencetext>Hi,Another possible solution is to use automated translation between C to VHDL or Verilog.
The website http://www.c-to-verilog.com is an open source project which gives you a compiler and an on-line service for compiling C to Verilog.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161127</id>
	<title>Ugly</title>
	<author>Anonymous</author>
	<datestamp>1243763880000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I learned VHDL at the University of Texas. It has got to be the ugliest language I've ever seen.</p></htmltext>
<tokenext>I learned VHDL at the University of Texas .
It has got to be the ugliest language I 've ever seen .</tokentext>
<sentencetext>I learned VHDL at the University of Texas.
It has got to be the ugliest language I've ever seen.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160385</id>
	<title>Re:Where are you located?</title>
	<author>drmerope</author>
	<datestamp>1243801920000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>2</modscore>
	<htmltext><p>I agree about the industry part, although I find it ironic since VHDL arose from DARPA funded work whereas Verilog is a proprietary innovation turned international standard.  At school I learned VHDL though.  This wasn't a problem when it came time to use Verilog at work.</p><p>My advice: cut against trend.  If you're a North American school, use VHDL.  If you're in Europe, use Verilog.  It may be the only chance for your students to taste the other side.</p><p>The insanity of VHDL is attaching two things that you know are 'just wires'.  In my experience you spend quite a lot of time writing type-conversion adapters.</p></htmltext>
<tokenext>I agree about the industry part , although I find it ironic since VHDL arose from DARPA funded work whereas Verilog is a proprietary innovation turned international standard .
At school I learned VHDL though .
This was n't a problem when it came time to use Verilog at work.My advice : cut against trend .
If you 're a North American school , use VHDL .
If you 're in Europe , use Verilog .
It may be the only chance for your students to taste the other side.The insanity of VHDL is attaching two things that you know are 'just wires' .
In my experience you spend quite a lot of time writing type-conversion adapters .</tokentext>
<sentencetext>I agree about the industry part, although I find it ironic since VHDL arose from DARPA funded work whereas Verilog is a proprietary innovation turned international standard.
At school I learned VHDL though.
This wasn't a problem when it came time to use Verilog at work.My advice: cut against trend.
If you're a North American school, use VHDL.
If you're in Europe, use Verilog.
It may be the only chance for your students to taste the other side.The insanity of VHDL is attaching two things that you know are 'just wires'.
In my experience you spend quite a lot of time writing type-conversion adapters.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159981</id>
	<title>Re:Where are you located?</title>
	<author>phulshof</author>
	<datestamp>1243798620000</datestamp>
	<modclass>Interestin</modclass>
	<modscore>5</modscore>
	<htmltext><p>I agree with the above post, though I personally prefer VHDL. That might however have something to do with me having designed ASIC/FPGAs for about 11 years now using VHDL though.<nobr> <wbr></nobr>:) Both are very powerful languages these days, and I see no problem in teaching a course using both languages, showing how to create the same hardware using different language constructs.</p></htmltext>
<tokenext>I agree with the above post , though I personally prefer VHDL .
That might however have something to do with me having designed ASIC/FPGAs for about 11 years now using VHDL though .
: ) Both are very powerful languages these days , and I see no problem in teaching a course using both languages , showing how to create the same hardware using different language constructs .</tokentext>
<sentencetext>I agree with the above post, though I personally prefer VHDL.
That might however have something to do with me having designed ASIC/FPGAs for about 11 years now using VHDL though.
:) Both are very powerful languages these days, and I see no problem in teaching a course using both languages, showing how to create the same hardware using different language constructs.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160161</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243800180000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><div class="quote"><p>In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.</p></div><p>When I worked at (UK-based processor designers) <a href="http://www.arm.com/" title="arm.com">ARM</a> [arm.com], Verilog was the language of choice. I've been told VHDL is popular in academia, while Verilog is more popular in industry.</p><p>That said, the underlying concepts are pretty similar, and those are what you're teaching really, so either choice would be reasonable.</p></div>
	</htmltext>
<tokenext>In industry , as far as I can tell , Verilog seems to be more used in North America and VHDL in Europe , so that might affect what you care about , too.When I worked at ( UK-based processor designers ) ARM [ arm.com ] , Verilog was the language of choice .
I 've been told VHDL is popular in academia , while Verilog is more popular in industry.That said , the underlying concepts are pretty similar , and those are what you 're teaching really , so either choice would be reasonable .</tokentext>
<sentencetext>In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.When I worked at (UK-based processor designers) ARM [arm.com], Verilog was the language of choice.
I've been told VHDL is popular in academia, while Verilog is more popular in industry.That said, the underlying concepts are pretty similar, and those are what you're teaching really, so either choice would be reasonable.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162451</id>
	<title>EDA tools</title>
	<author>dmesg0</author>
	<datestamp>1243775760000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>It isn't a secret in the EDA industry that VHDL gets much less developers attention than Verilog and SystemVerilog. In some products VHDL gets probably 1/5th time of Verilog and 1/20 of SystemVerilog (into which most resources are invested). Although the differences might be less striking in other fields, e.g. FPGA-related, it is still there.

This leads to lower performance, bugs going unfixed for quite long time, few new features etc. So my recommendation would be to go with the market leader - Verilog.</htmltext>
<tokenext>It is n't a secret in the EDA industry that VHDL gets much less developers attention than Verilog and SystemVerilog .
In some products VHDL gets probably 1/5th time of Verilog and 1/20 of SystemVerilog ( into which most resources are invested ) .
Although the differences might be less striking in other fields , e.g .
FPGA-related , it is still there .
This leads to lower performance , bugs going unfixed for quite long time , few new features etc .
So my recommendation would be to go with the market leader - Verilog .</tokentext>
<sentencetext>It isn't a secret in the EDA industry that VHDL gets much less developers attention than Verilog and SystemVerilog.
In some products VHDL gets probably 1/5th time of Verilog and 1/20 of SystemVerilog (into which most resources are invested).
Although the differences might be less striking in other fields, e.g.
FPGA-related, it is still there.
This leads to lower performance, bugs going unfixed for quite long time, few new features etc.
So my recommendation would be to go with the market leader - Verilog.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163335</id>
	<title>VHDL</title>
	<author>Anonymous</author>
	<datestamp>1243783440000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>*) THIS is a "holy war"</p><p>*) this means that my opinion is biased. But I live with it and even get things done !</p><p>*) VHDL is a dog, is prone to syntax nazism and looks bloated.</p><p>*) However VHDL is incredibly powerful, like PERL gone syntax nazy. You can do one thing 3 or 4 ways, as you like (when you know the several ways).  This means that VHDL can do<nobr> <wbr></nobr>/anything/. Even a web server<nobr> <wbr></nobr>;-D</p><p>*) Now, Verilog (in my perspective) is nice to get "things done" like in C. But like C it trades compactness and writing speed for clarity and stability.</p></htmltext>
<tokenext>* ) THIS is a " holy war " * ) this means that my opinion is biased .
But I live with it and even get things done !
* ) VHDL is a dog , is prone to syntax nazism and looks bloated .
* ) However VHDL is incredibly powerful , like PERL gone syntax nazy .
You can do one thing 3 or 4 ways , as you like ( when you know the several ways ) .
This means that VHDL can do /anything/ .
Even a web server ; -D * ) Now , Verilog ( in my perspective ) is nice to get " things done " like in C. But like C it trades compactness and writing speed for clarity and stability .</tokentext>
<sentencetext>*) THIS is a "holy war"*) this means that my opinion is biased.
But I live with it and even get things done !
*) VHDL is a dog, is prone to syntax nazism and looks bloated.
*) However VHDL is incredibly powerful, like PERL gone syntax nazy.
You can do one thing 3 or 4 ways, as you like (when you know the several ways).
This means that VHDL can do /anything/.
Even a web server ;-D*) Now, Verilog (in my perspective) is nice to get "things done" like in C. But like C it trades compactness and writing speed for clarity and stability.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</id>
	<title>Re:Where are you located?</title>
	<author>Man On Pink Corner</author>
	<datestamp>1243799880000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>5</modscore>
	<htmltext><p>Speaking as someone who just got his first Verilog-based design working on a Nexys2 board, I can confidently say that there are two serious mistakes a n00b can make:</p><p>1) Thinking of Verilog (or any HDL) as anything like C.  Yes, there are semicolons.  Yes, you can write a "for" loop, if you want to synthesize a huge mess.  That's about it.</p><p>2) Thinking of Verilog as a programming language at all.  HDL stands for "Hardware description language," and that's what they are.</p><p>Verilog is fun stuff, but it's the hardest thing I've ever taught myself.  For those who are trying, I've found the Bhasker books on synthesis to be quite useful, Pong Chu's <i>FPGA Prototyping with Verilog Examples</i> to be reasonably useful, and most of the others to be fairly worthless.  Too many books focus on simulation at the expense of synthesis practices, IMO.</p><p>Also have just received Richard Haskell's new <a href="http://www.lbebooks.com/booksandkits.htm" title="lbebooks.com">books</a> [lbebooks.com] on basic and advanced Verilog using the Basys and Nexys2 platforms.  They look very good at first glance but I haven't yet had a lot of time to spend with either of them.</p></htmltext>
<tokenext>Speaking as someone who just got his first Verilog-based design working on a Nexys2 board , I can confidently say that there are two serious mistakes a n00b can make : 1 ) Thinking of Verilog ( or any HDL ) as anything like C. Yes , there are semicolons .
Yes , you can write a " for " loop , if you want to synthesize a huge mess .
That 's about it.2 ) Thinking of Verilog as a programming language at all .
HDL stands for " Hardware description language , " and that 's what they are.Verilog is fun stuff , but it 's the hardest thing I 've ever taught myself .
For those who are trying , I 've found the Bhasker books on synthesis to be quite useful , Pong Chu 's FPGA Prototyping with Verilog Examples to be reasonably useful , and most of the others to be fairly worthless .
Too many books focus on simulation at the expense of synthesis practices , IMO.Also have just received Richard Haskell 's new books [ lbebooks.com ] on basic and advanced Verilog using the Basys and Nexys2 platforms .
They look very good at first glance but I have n't yet had a lot of time to spend with either of them .</tokentext>
<sentencetext>Speaking as someone who just got his first Verilog-based design working on a Nexys2 board, I can confidently say that there are two serious mistakes a n00b can make:1) Thinking of Verilog (or any HDL) as anything like C.  Yes, there are semicolons.
Yes, you can write a "for" loop, if you want to synthesize a huge mess.
That's about it.2) Thinking of Verilog as a programming language at all.
HDL stands for "Hardware description language," and that's what they are.Verilog is fun stuff, but it's the hardest thing I've ever taught myself.
For those who are trying, I've found the Bhasker books on synthesis to be quite useful, Pong Chu's FPGA Prototyping with Verilog Examples to be reasonably useful, and most of the others to be fairly worthless.
Too many books focus on simulation at the expense of synthesis practices, IMO.Also have just received Richard Haskell's new books [lbebooks.com] on basic and advanced Verilog using the Basys and Nexys2 platforms.
They look very good at first glance but I haven't yet had a lot of time to spend with either of them.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28167449</id>
	<title>Re:System Verilog</title>
	<author>imgod2u</author>
	<datestamp>1243868640000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext><p>That is a very dangerous idea. "Let them be sloppy and still make their thing work" may work for software -- where you can just release a patch to fix problems that pop up -- but the primary and most important thing about ASIC design is <b>you only get one shot at it</b>.</p><p>That's the first lesson hardware design courses should be teaching. Not making them feel good about how their non-functioning Verilog "program" actually compiles. By the time they actually program it into the FPGA, they should've understood fully how it would translate into gates by the synthesis tool and how it would translate into device-specific macros by the place and route tool.</p><p>They should've simulated it at all points of translation as well. VHDL forces you to do this to an extent and that's a <b>good</b> thing.</p></htmltext>
<tokenext>That is a very dangerous idea .
" Let them be sloppy and still make their thing work " may work for software -- where you can just release a patch to fix problems that pop up -- but the primary and most important thing about ASIC design is you only get one shot at it.That 's the first lesson hardware design courses should be teaching .
Not making them feel good about how their non-functioning Verilog " program " actually compiles .
By the time they actually program it into the FPGA , they should 've understood fully how it would translate into gates by the synthesis tool and how it would translate into device-specific macros by the place and route tool.They should 've simulated it at all points of translation as well .
VHDL forces you to do this to an extent and that 's a good thing .</tokentext>
<sentencetext>That is a very dangerous idea.
"Let them be sloppy and still make their thing work" may work for software -- where you can just release a patch to fix problems that pop up -- but the primary and most important thing about ASIC design is you only get one shot at it.That's the first lesson hardware design courses should be teaching.
Not making them feel good about how their non-functioning Verilog "program" actually compiles.
By the time they actually program it into the FPGA, they should've understood fully how it would translate into gates by the synthesis tool and how it would translate into device-specific macros by the place and route tool.They should've simulated it at all points of translation as well.
VHDL forces you to do this to an extent and that's a good thing.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160761</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162267</id>
	<title>Re:Where are you located?</title>
	<author>PSargent</author>
	<datestamp>1243774140000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Yep, this is the right attitude. Use the language that has the type checking and strict structure, and then when the shackles come off people have already formed good habits.</p><p>I've done about 8 years of VHDL and so prefer it to Verilog, mainly because I'm more familiar with it, but I've had lots of conversations with Verilog engineers over the years saying "You can't do X with VHDL because it's too strict" and it's never true. Learning VHDL was tough, but doing it (and I've got a similar tale with Haskell for software) was what advanced my skills of RTL coding the most.</p><p>The key is not to fight the restrictions, but to understand why they are there and to see what they allow you to forget about. It's sounds almost zen, but sometimes restrictions let you flow.<nobr> <wbr></nobr>...but never forget. The aim is to describe hardware, so you need to have in mind what hardware you want to synth at the end of the day. As such the language is always second to good hardware  design.</p></htmltext>
<tokenext>Yep , this is the right attitude .
Use the language that has the type checking and strict structure , and then when the shackles come off people have already formed good habits.I 've done about 8 years of VHDL and so prefer it to Verilog , mainly because I 'm more familiar with it , but I 've had lots of conversations with Verilog engineers over the years saying " You ca n't do X with VHDL because it 's too strict " and it 's never true .
Learning VHDL was tough , but doing it ( and I 've got a similar tale with Haskell for software ) was what advanced my skills of RTL coding the most.The key is not to fight the restrictions , but to understand why they are there and to see what they allow you to forget about .
It 's sounds almost zen , but sometimes restrictions let you flow .
...but never forget .
The aim is to describe hardware , so you need to have in mind what hardware you want to synth at the end of the day .
As such the language is always second to good hardware design .</tokentext>
<sentencetext>Yep, this is the right attitude.
Use the language that has the type checking and strict structure, and then when the shackles come off people have already formed good habits.I've done about 8 years of VHDL and so prefer it to Verilog, mainly because I'm more familiar with it, but I've had lots of conversations with Verilog engineers over the years saying "You can't do X with VHDL because it's too strict" and it's never true.
Learning VHDL was tough, but doing it (and I've got a similar tale with Haskell for software) was what advanced my skills of RTL coding the most.The key is not to fight the restrictions, but to understand why they are there and to see what they allow you to forget about.
It's sounds almost zen, but sometimes restrictions let you flow.
...but never forget.
The aim is to describe hardware, so you need to have in mind what hardware you want to synth at the end of the day.
As such the language is always second to good hardware  design.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165273</id>
	<title>Re:Where are you located?</title>
	<author>Man On Pink Corner</author>
	<datestamp>1243847820000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p><i>As someone who has spent A LOT of time using both in university, I would say Verilog is the easiest to learn because its syntax is very closely related to C.</i></p><p>Doing FPGA or ASIC designs?</p><p><i>1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.</i></p><p>Syntax doth not a language make.</p></htmltext>
<tokenext>As someone who has spent A LOT of time using both in university , I would say Verilog is the easiest to learn because its syntax is very closely related to C.Doing FPGA or ASIC designs ? 1 ) The syntax is incredibly similar to C. Which is why it is always described as " C like " to people who have very little experience in HDL.Syntax doth not a language make .</tokentext>
<sentencetext>As someone who has spent A LOT of time using both in university, I would say Verilog is the easiest to learn because its syntax is very closely related to C.Doing FPGA or ASIC designs?1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.Syntax doth not a language make.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161031</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160953</id>
	<title>Quartus - VDHL / Verilog</title>
	<author>Murdoch5</author>
	<datestamp>1243762380000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>I have to mention this because I think it's important, well you can find programs for helping with HDL there is one I have to point out Quartus, it's probley the most broken program for doing HDL.
It seems fitting that if your going to ask the question Verilog or Vhdl you need to also look at what your going to use to program these.  In college we had to use a program called Quartus from <p><div class="quote"><p>http://www.altera.com/products/software/quartus-ii/subscription-edition/qts-se-index.html</p></div><p>
Everything we ever tried to do using Quartus was overly hard.  Every time we needed to assign pins or select a device Quartus would either fail or it's servers JTAG would crash or we'd have to reboot Windows.  I don't want to rip this appear but as a moral and ethical person I had to inform you of this.
<br>
<br>
Quartus can help with Vhdl and Verilog for sure. I'm not saying it can't but everything you'll ever do with it is made 10 x harder and more complex then it ever has to be.   If you going to teach students make sure to say away from this software!</p></div>
	</htmltext>
<tokenext>I have to mention this because I think it 's important , well you can find programs for helping with HDL there is one I have to point out Quartus , it 's probley the most broken program for doing HDL .
It seems fitting that if your going to ask the question Verilog or Vhdl you need to also look at what your going to use to program these .
In college we had to use a program called Quartus from http : //www.altera.com/products/software/quartus-ii/subscription-edition/qts-se-index.html Everything we ever tried to do using Quartus was overly hard .
Every time we needed to assign pins or select a device Quartus would either fail or it 's servers JTAG would crash or we 'd have to reboot Windows .
I do n't want to rip this appear but as a moral and ethical person I had to inform you of this .
Quartus can help with Vhdl and Verilog for sure .
I 'm not saying it ca n't but everything you 'll ever do with it is made 10 x harder and more complex then it ever has to be .
If you going to teach students make sure to say away from this software !</tokentext>
<sentencetext>I have to mention this because I think it's important, well you can find programs for helping with HDL there is one I have to point out Quartus, it's probley the most broken program for doing HDL.
It seems fitting that if your going to ask the question Verilog or Vhdl you need to also look at what your going to use to program these.
In college we had to use a program called Quartus from http://www.altera.com/products/software/quartus-ii/subscription-edition/qts-se-index.html
Everything we ever tried to do using Quartus was overly hard.
Every time we needed to assign pins or select a device Quartus would either fail or it's servers JTAG would crash or we'd have to reboot Windows.
I don't want to rip this appear but as a moral and ethical person I had to inform you of this.
Quartus can help with Vhdl and Verilog for sure.
I'm not saying it can't but everything you'll ever do with it is made 10 x harder and more complex then it ever has to be.
If you going to teach students make sure to say away from this software!
	</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28168833</id>
	<title>Re:I like VHDL... Here are some cool reasons why.</title>
	<author>Anonymous</author>
	<datestamp>1243874580000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p><div class="quote"><p>Disclaimer #1:   I work for Xilinx.   Disclaimer #2:  I used to teach VHDL, back in the late 90's.    I too, voted on the IEEE effort for standardization on the synthesizable subset for VHDL, and boy what a waste of time that was.  But I digress.   Here are some cool reasons why VHDL is better than Verilog. </p><p>
&nbsp; &nbsp; &nbsp; 1.  Recursion.  You can write recursive hardware components that instantiate smaller versions of themselves.    Recursion is cool, but tools hate it.   The Xilinx tools complain about it, but will still produce the right hardware.   Recursion can be used for Multipliers, adder trees, priority encoders, muxes, and just about anything where divide and conquer actually works.</p></div><p>Exactly why you should not use it. With FPGAs you may be able to get way with relaying on the synthesis tool to understand your intent but ASIC tools have a MUCH harder job. They cannot be optimized for the target library and have other things to worry about like clock-gating. An ASIC designer should assume the worst from the tool. There are also FV issues.</p><p><div class="quote"><p>   2.  Attributes.  VHDL attributes translate straight to EDIF properties, and let you do cool stuff like physical design in an FPGA,  EDIF properties in the netlist let you do anything from selecting the power-on state of a flop, to setting the logic function of a lookup table (LUT), or setting the initial value of a RAM.  Even better, you can pass LOC (Location) or RLOC (relative location) properties, allowing you to physically place the location of a component in the target device.  You can even specify directed routing constraints that lock down the signal path to a specific defined route.   Verilog will sort of let you do this, but only in a pragma (code comment).  Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL, but not in Verilog.</p></div><p>Physical constraints should not be in the RTL. This coding style is endemic in FPGA designs I've noticed. In ASIC flows a separate engineer is usually responsible for layout and he/she will greatly frown upon these.</p><p>
&nbsp; &nbsp; </p><p><div class="quote"><p>  3.  Compile time elaboration of constants.   This sounds incredibly obscure, but is actually very powerful.  During elaboration, constants are evaluated.  Constants can be defined by an arbitrarily complex function call.    These functions can perform arbitrary computation, as well as read and write files.   A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM.   I use compile time function calls to do precomputation on stuff where I don't know the generic parameters in advance.   An example of this would be a state machine to detect a serial unique word, with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter.   Or how about CRC's?   You see people writing C programs to generate Verilog designs to calculate a CRC, but in VHDL, you can compute the parity matrices directly at compile time given a static CRC as a generic parameter.  Once the parity matrix is generated, it's easy to generate the hardware to calculate it.   It's a bit trickier to do error correction with a CRC, but also possible.   These calculations are hideously difficult in Verilog.</p></div><p>Things like compile-time constant calculations will drive validation engineers nuts. Why would you not calculate the constants once with an external script, then set it in your design? I find your statement interesting because ISE has many code generators which do exactly that. </p><p>
&nbsp; &nbsp; Verilog can very easily initialize memory from a file. However most ASICs do not support this so it is usually done to support validation.</p><p>
&nbsp; &nbsp; Again the right tool for the job. Verilog/VHDL should model the logic, not support the calculation of any arbitrary function. This just makes things harder for the synthesis tools which have enough bugs as it is.</p><p>
&nbsp; </p><p><div class="quote"><p>  4.  Type REAL.   VHDL has a floating data type REAL, and even a IEEE library REALMATH to use it with (Sine, Cosine, Tangent, etc).  You can do very nice geometry calculations during elaboration with this library.   Or, for the EE's, you can do stuff like generate coefficents for a raised root cosine filter in VHDL.   Now REAL types can't be synthesized directly, since they have no direct hardware representation.. but REAL can be converted to INTEGERs, and integers can be turned in to real hardware with a precision of up to 32 bits.  That's plenty in most cases in an FPGA.</p></div><p>None of which should ever appear in synthesized code. For testing purposes I'd argue both VHDL and Verilog are not up to the task.</p></div>
	</htmltext>
<tokenext>Disclaimer # 1 : I work for Xilinx .
Disclaimer # 2 : I used to teach VHDL , back in the late 90 's .
I too , voted on the IEEE effort for standardization on the synthesizable subset for VHDL , and boy what a waste of time that was .
But I digress .
Here are some cool reasons why VHDL is better than Verilog .
      1 .
Recursion. You can write recursive hardware components that instantiate smaller versions of themselves .
Recursion is cool , but tools hate it .
The Xilinx tools complain about it , but will still produce the right hardware .
Recursion can be used for Multipliers , adder trees , priority encoders , muxes , and just about anything where divide and conquer actually works.Exactly why you should not use it .
With FPGAs you may be able to get way with relaying on the synthesis tool to understand your intent but ASIC tools have a MUCH harder job .
They can not be optimized for the target library and have other things to worry about like clock-gating .
An ASIC designer should assume the worst from the tool .
There are also FV issues .
2. Attributes .
VHDL attributes translate straight to EDIF properties , and let you do cool stuff like physical design in an FPGA , EDIF properties in the netlist let you do anything from selecting the power-on state of a flop , to setting the logic function of a lookup table ( LUT ) , or setting the initial value of a RAM .
Even better , you can pass LOC ( Location ) or RLOC ( relative location ) properties , allowing you to physically place the location of a component in the target device .
You can even specify directed routing constraints that lock down the signal path to a specific defined route .
Verilog will sort of let you do this , but only in a pragma ( code comment ) .
Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL , but not in Verilog.Physical constraints should not be in the RTL .
This coding style is endemic in FPGA designs I 've noticed .
In ASIC flows a separate engineer is usually responsible for layout and he/she will greatly frown upon these .
    3 .
Compile time elaboration of constants .
This sounds incredibly obscure , but is actually very powerful .
During elaboration , constants are evaluated .
Constants can be defined by an arbitrarily complex function call .
These functions can perform arbitrary computation , as well as read and write files .
A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM .
I use compile time function calls to do precomputation on stuff where I do n't know the generic parameters in advance .
An example of this would be a state machine to detect a serial unique word , with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter .
Or how about CRC 's ?
You see people writing C programs to generate Verilog designs to calculate a CRC , but in VHDL , you can compute the parity matrices directly at compile time given a static CRC as a generic parameter .
Once the parity matrix is generated , it 's easy to generate the hardware to calculate it .
It 's a bit trickier to do error correction with a CRC , but also possible .
These calculations are hideously difficult in Verilog.Things like compile-time constant calculations will drive validation engineers nuts .
Why would you not calculate the constants once with an external script , then set it in your design ?
I find your statement interesting because ISE has many code generators which do exactly that .
    Verilog can very easily initialize memory from a file .
However most ASICs do not support this so it is usually done to support validation .
    Again the right tool for the job .
Verilog/VHDL should model the logic , not support the calculation of any arbitrary function .
This just makes things harder for the synthesis tools which have enough bugs as it is .
  4 .
Type REAL .
VHDL has a floating data type REAL , and even a IEEE library REALMATH to use it with ( Sine , Cosine , Tangent , etc ) .
You can do very nice geometry calculations during elaboration with this library .
Or , for the EE 's , you can do stuff like generate coefficents for a raised root cosine filter in VHDL .
Now REAL types ca n't be synthesized directly , since they have no direct hardware representation.. but REAL can be converted to INTEGERs , and integers can be turned in to real hardware with a precision of up to 32 bits .
That 's plenty in most cases in an FPGA.None of which should ever appear in synthesized code .
For testing purposes I 'd argue both VHDL and Verilog are not up to the task .</tokentext>
<sentencetext>Disclaimer #1:   I work for Xilinx.
Disclaimer #2:  I used to teach VHDL, back in the late 90's.
I too, voted on the IEEE effort for standardization on the synthesizable subset for VHDL, and boy what a waste of time that was.
But I digress.
Here are some cool reasons why VHDL is better than Verilog.
      1.
Recursion.  You can write recursive hardware components that instantiate smaller versions of themselves.
Recursion is cool, but tools hate it.
The Xilinx tools complain about it, but will still produce the right hardware.
Recursion can be used for Multipliers, adder trees, priority encoders, muxes, and just about anything where divide and conquer actually works.Exactly why you should not use it.
With FPGAs you may be able to get way with relaying on the synthesis tool to understand your intent but ASIC tools have a MUCH harder job.
They cannot be optimized for the target library and have other things to worry about like clock-gating.
An ASIC designer should assume the worst from the tool.
There are also FV issues.
2.  Attributes.
VHDL attributes translate straight to EDIF properties, and let you do cool stuff like physical design in an FPGA,  EDIF properties in the netlist let you do anything from selecting the power-on state of a flop, to setting the logic function of a lookup table (LUT), or setting the initial value of a RAM.
Even better, you can pass LOC (Location) or RLOC (relative location) properties, allowing you to physically place the location of a component in the target device.
You can even specify directed routing constraints that lock down the signal path to a specific defined route.
Verilog will sort of let you do this, but only in a pragma (code comment).
Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL, but not in Verilog.Physical constraints should not be in the RTL.
This coding style is endemic in FPGA designs I've noticed.
In ASIC flows a separate engineer is usually responsible for layout and he/she will greatly frown upon these.
      3.
Compile time elaboration of constants.
This sounds incredibly obscure, but is actually very powerful.
During elaboration, constants are evaluated.
Constants can be defined by an arbitrarily complex function call.
These functions can perform arbitrary computation, as well as read and write files.
A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM.
I use compile time function calls to do precomputation on stuff where I don't know the generic parameters in advance.
An example of this would be a state machine to detect a serial unique word, with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter.
Or how about CRC's?
You see people writing C programs to generate Verilog designs to calculate a CRC, but in VHDL, you can compute the parity matrices directly at compile time given a static CRC as a generic parameter.
Once the parity matrix is generated, it's easy to generate the hardware to calculate it.
It's a bit trickier to do error correction with a CRC, but also possible.
These calculations are hideously difficult in Verilog.Things like compile-time constant calculations will drive validation engineers nuts.
Why would you not calculate the constants once with an external script, then set it in your design?
I find your statement interesting because ISE has many code generators which do exactly that.
    Verilog can very easily initialize memory from a file.
However most ASICs do not support this so it is usually done to support validation.
    Again the right tool for the job.
Verilog/VHDL should model the logic, not support the calculation of any arbitrary function.
This just makes things harder for the synthesis tools which have enough bugs as it is.
    4.
Type REAL.
VHDL has a floating data type REAL, and even a IEEE library REALMATH to use it with (Sine, Cosine, Tangent, etc).
You can do very nice geometry calculations during elaboration with this library.
Or, for the EE's, you can do stuff like generate coefficents for a raised root cosine filter in VHDL.
Now REAL types can't be synthesized directly, since they have no direct hardware representation.. but REAL can be converted to INTEGERs, and integers can be turned in to real hardware with a precision of up to 32 bits.
That's plenty in most cases in an FPGA.None of which should ever appear in synthesized code.
For testing purposes I'd argue both VHDL and Verilog are not up to the task.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162127</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161939</id>
	<title>Personal experience</title>
	<author>AlecC</author>
	<datestamp>1243771320000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>As a pure software geek working in a hardware environment, VHDL is prerferred. But equally - of it works, go with it. Verilog is accepted as valid as VHDL.</p></htmltext>
<tokenext>As a pure software geek working in a hardware environment , VHDL is prerferred .
But equally - of it works , go with it .
Verilog is accepted as valid as VHDL .</tokentext>
<sentencetext>As a pure software geek working in a hardware environment, VHDL is prerferred.
But equally - of it works, go with it.
Verilog is accepted as valid as VHDL.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161071</id>
	<title>VHDL=ADA, Verilog=C</title>
	<author>RKBA</author>
	<datestamp>1243763400000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>If you like the ADA programming language (Yuk!), then choose VHDL. If you prefer the C programming language, then choose Verilog.</p></htmltext>
<tokenext>If you like the ADA programming language ( Yuk !
) , then choose VHDL .
If you prefer the C programming language , then choose Verilog .</tokentext>
<sentencetext>If you like the ADA programming language (Yuk!
), then choose VHDL.
If you prefer the C programming language, then choose Verilog.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28167651</id>
	<title>I recommend teaching both VHDL and Verilog</title>
	<author>kojot350</author>
	<datestamp>1243869360000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext>Consider teaching both. I'm a student and I've used VHDL in first semester and Verilog in second (a project). I've found very good book for students/beginners and it was fun to learn it with it, the book was Digital design and computer architecture By David Money Harris, Sarah L. Harris.

<a href="http://books.google.com/books?id=5X7JV5-n0FIC&amp;dq=digital+design+and+computer+architecture+solutions&amp;printsec=frontcover&amp;source=bn&amp;hl=en&amp;ei=T-EjSqP3NoWNjAe53b2rBg&amp;sa=X&amp;oi=book\_result&amp;ct=result&amp;resnum=4" title="google.com" rel="nofollow">http://books.google.com/books?id=5X7JV5-n0FIC&amp;dq=digital+design+and+computer+architecture+solutions&amp;printsec=frontcover&amp;source=bn&amp;hl=en&amp;ei=T-EjSqP3NoWNjAe53b2rBg&amp;sa=X&amp;oi=book\_result&amp;ct=result&amp;resnum=4</a> [google.com]</htmltext>
<tokenext>Consider teaching both .
I 'm a student and I 've used VHDL in first semester and Verilog in second ( a project ) .
I 've found very good book for students/beginners and it was fun to learn it with it , the book was Digital design and computer architecture By David Money Harris , Sarah L. Harris . http : //books.google.com/books ? id = 5X7JV5-n0FIC&amp;dq = digital + design + and + computer + architecture + solutions&amp;printsec = frontcover&amp;source = bn&amp;hl = en&amp;ei = T-EjSqP3NoWNjAe53b2rBg&amp;sa = X&amp;oi = book \ _result&amp;ct = result&amp;resnum = 4 [ google.com ]</tokentext>
<sentencetext>Consider teaching both.
I'm a student and I've used VHDL in first semester and Verilog in second (a project).
I've found very good book for students/beginners and it was fun to learn it with it, the book was Digital design and computer architecture By David Money Harris, Sarah L. Harris.

http://books.google.com/books?id=5X7JV5-n0FIC&amp;dq=digital+design+and+computer+architecture+solutions&amp;printsec=frontcover&amp;source=bn&amp;hl=en&amp;ei=T-EjSqP3NoWNjAe53b2rBg&amp;sa=X&amp;oi=book\_result&amp;ct=result&amp;resnum=4 [google.com]</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161161</id>
	<title>Dont assume previous knowledge</title>
	<author>Anonymous</author>
	<datestamp>1243764360000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I have already taken a Digital Systems Design class and we used the exact same Spartan FPGA board.  I am a freshman at the University of Cincinnati, and they made one very large mistake when scheduling this course.  We were required to take this course before taking our introductory to C++ course.  This made learning Verilog extremely difficult having had no programming background and the teacher was assuming that we all knew C pretty well.  The book we used was Digital Design by Mano and Ciletti.  It was a rough course for my classmates and I but I'd be interested in hearing your ideas to teach the course.  Of course the only other downside is now that I am past the course I'm stuck with a $70 FPGA board that I'm sick of looking at.  Overall I would suggest focusing more on Verilog instead of VHDL.</p></htmltext>
<tokenext>I have already taken a Digital Systems Design class and we used the exact same Spartan FPGA board .
I am a freshman at the University of Cincinnati , and they made one very large mistake when scheduling this course .
We were required to take this course before taking our introductory to C + + course .
This made learning Verilog extremely difficult having had no programming background and the teacher was assuming that we all knew C pretty well .
The book we used was Digital Design by Mano and Ciletti .
It was a rough course for my classmates and I but I 'd be interested in hearing your ideas to teach the course .
Of course the only other downside is now that I am past the course I 'm stuck with a $ 70 FPGA board that I 'm sick of looking at .
Overall I would suggest focusing more on Verilog instead of VHDL .</tokentext>
<sentencetext>I have already taken a Digital Systems Design class and we used the exact same Spartan FPGA board.
I am a freshman at the University of Cincinnati, and they made one very large mistake when scheduling this course.
We were required to take this course before taking our introductory to C++ course.
This made learning Verilog extremely difficult having had no programming background and the teacher was assuming that we all knew C pretty well.
The book we used was Digital Design by Mano and Ciletti.
It was a rough course for my classmates and I but I'd be interested in hearing your ideas to teach the course.
Of course the only other downside is now that I am past the course I'm stuck with a $70 FPGA board that I'm sick of looking at.
Overall I would suggest focusing more on Verilog instead of VHDL.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163063</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243780920000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>All inclusive summary of comments.  Close thread, mod up...  and good night people!</p></htmltext>
<tokenext>All inclusive summary of comments .
Close thread , mod up... and good night people !</tokentext>
<sentencetext>All inclusive summary of comments.
Close thread, mod up...  and good night people!</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28170253</id>
	<title>Re:Where are you located?</title>
	<author>Mister\_Stoopid</author>
	<datestamp>1243880940000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Agreed Xilinx software is pretty quirky and buggy.  All I want is support for spaces in filenames/paths!  Is that so much to ask? IS IT?!?

That said, things have come a long way since I was in school and it's not nearly as disorganized/crashy as it was back then.</htmltext>
<tokenext>Agreed Xilinx software is pretty quirky and buggy .
All I want is support for spaces in filenames/paths !
Is that so much to ask ?
IS IT ? ! ?
That said , things have come a long way since I was in school and it 's not nearly as disorganized/crashy as it was back then .</tokentext>
<sentencetext>Agreed Xilinx software is pretty quirky and buggy.
All I want is support for spaces in filenames/paths!
Is that so much to ask?
IS IT?!?
That said, things have come a long way since I was in school and it's not nearly as disorganized/crashy as it was back then.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160377</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161183</id>
	<title>Xilinx software</title>
	<author>OutputLogic</author>
	<datestamp>1243764540000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext>How is this info relevant in 2009 ?

I've been working with Xilinx in the last 9 years and can attest that their software has a decent quality. By "decent" I mean no better or worse that its competitor Altera. There are occasional bugs which are quickly fixed or tech support offers a work-around.
<br> <br>
Thanks
<br>
Visit <a href="http://outputlogic.com/" title="outputlogic.com" rel="nofollow">http://outputlogic.com/</a> [outputlogic.com]  : tools that improve productivity</htmltext>
<tokenext>How is this info relevant in 2009 ?
I 've been working with Xilinx in the last 9 years and can attest that their software has a decent quality .
By " decent " I mean no better or worse that its competitor Altera .
There are occasional bugs which are quickly fixed or tech support offers a work-around .
Thanks Visit http : //outputlogic.com/ [ outputlogic.com ] : tools that improve productivity</tokentext>
<sentencetext>How is this info relevant in 2009 ?
I've been working with Xilinx in the last 9 years and can attest that their software has a decent quality.
By "decent" I mean no better or worse that its competitor Altera.
There are occasional bugs which are quickly fixed or tech support offers a work-around.
Thanks

Visit http://outputlogic.com/ [outputlogic.com]  : tools that improve productivity</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160377</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160327</id>
	<title>Re:Where are you located?</title>
	<author>arktemplar</author>
	<datestamp>1243801380000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Yes, essentially I'd agree with you.</p><p>However the thing is this, it's easier to get synthesiseable code in verilog that will correspond to your code directly, if you have experience, that is. However, VHDL seems to be better in my opinion only because it is more structured.</p><p>Ok - so the thing is, I've done significant work in both. I kind of liked the fact that VHDL was more structured and readable, however Verilog seems to have more support. Now, apart from this the differences, are mostly in getting synthesiseable results from your code, it's easier to get code match the RTL, like I've already said, if you're working in Verilog, plus synthesisers also have better support for Verilog. However, after getting started on verilog, VHDL is much more attractive in my opinion.</p></htmltext>
<tokenext>Yes , essentially I 'd agree with you.However the thing is this , it 's easier to get synthesiseable code in verilog that will correspond to your code directly , if you have experience , that is .
However , VHDL seems to be better in my opinion only because it is more structured.Ok - so the thing is , I 've done significant work in both .
I kind of liked the fact that VHDL was more structured and readable , however Verilog seems to have more support .
Now , apart from this the differences , are mostly in getting synthesiseable results from your code , it 's easier to get code match the RTL , like I 've already said , if you 're working in Verilog , plus synthesisers also have better support for Verilog .
However , after getting started on verilog , VHDL is much more attractive in my opinion .</tokentext>
<sentencetext>Yes, essentially I'd agree with you.However the thing is this, it's easier to get synthesiseable code in verilog that will correspond to your code directly, if you have experience, that is.
However, VHDL seems to be better in my opinion only because it is more structured.Ok - so the thing is, I've done significant work in both.
I kind of liked the fact that VHDL was more structured and readable, however Verilog seems to have more support.
Now, apart from this the differences, are mostly in getting synthesiseable results from your code, it's easier to get code match the RTL, like I've already said, if you're working in Verilog, plus synthesisers also have better support for Verilog.
However, after getting started on verilog, VHDL is much more attractive in my opinion.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160679</id>
	<title>For what its worth</title>
	<author>427\_ci\_505</author>
	<datestamp>1243760580000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I've only ever used VHDL, but it is fairly clean and easy to get started with.</p><p>I suppose I should have given Verilog more of a chance, but I just ran away screaming whenever I opened up a *.v file.</p></htmltext>
<tokenext>I 've only ever used VHDL , but it is fairly clean and easy to get started with.I suppose I should have given Verilog more of a chance , but I just ran away screaming whenever I opened up a * .v file .</tokentext>
<sentencetext>I've only ever used VHDL, but it is fairly clean and easy to get started with.I suppose I should have given Verilog more of a chance, but I just ran away screaming whenever I opened up a *.v file.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162299</id>
	<title>What I've seen in NA</title>
	<author>CertGen</author>
	<datestamp>1243774440000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I work for an FPGA company. Both languages are going strong. You'd do well to learn both. My experience says if you want to work in government, especially military, it's pretty much dominated by VHDL. And Verilog is the prevalent language in telco and video design.</htmltext>
<tokenext>I work for an FPGA company .
Both languages are going strong .
You 'd do well to learn both .
My experience says if you want to work in government , especially military , it 's pretty much dominated by VHDL .
And Verilog is the prevalent language in telco and video design .</tokentext>
<sentencetext>I work for an FPGA company.
Both languages are going strong.
You'd do well to learn both.
My experience says if you want to work in government, especially military, it's pretty much dominated by VHDL.
And Verilog is the prevalent language in telco and video design.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160837</id>
	<title>Probably Verilog</title>
	<author>davebaum</author>
	<datestamp>1243761600000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext><p>VHDL and Verilog each have their strengths, which is why neither has been able to supplant the other.  Perhaps in the long run System Verilog will change this (bringing much of the power of VHDL to the Verilog world), but that day hasn't arrived yet.</p><p>
&nbsp; </p><p>Verilog code tends to be very concise, with the language making some implicit conversions and assumptions that turn out to be correct most of the time.</p><p>
&nbsp; </p><p>VHDL is bigger, bulkier and more rigid.  The rigidity can be annoying, but it also is good at catching errors.  The language has features that allow for very elaborate testbench construction, and some powerful means for abstraction (the generate statement, multiple architectures for an entity, etc).  But this power comes at a cost.  The spec for the language is several times larger than for VHDL.  At one point I had a Verilog quick reference that fit nicely on a single page.  My equivalent quick reference for VHDL covered four pages.</p><p>
&nbsp; </p><p>I've gone through the "choose an HDL" process twice, and both times selected VHDL.  But that was within the context of at least half the team already being fluent in VHDL, and working on a large enough (and long lived enough) codebase that we could take advantage of some of VHDL's power.  I wish VHDL wasn't so cumbersome and verbose, but it was still a win overall.</p><p>
&nbsp; </p><p>You are in a very different situation.  I'm assuming you have minimal experience with either language, and it will be new to your students as well.  You're going to have plenty of other things to be worrying about (digital design, synthesis, debugging, etc).  I think Verilog is a better choice for your situation.  It's going to do everything you need, and not really get in your way.</p><p>
&nbsp; </p><p>Also, don't worry about which tool is more popular in industry.  Tools change many times over a career.  University classes should be about providing good theory and foundation, so pick whatever tool enables you teach those concepts most effectively.</p></htmltext>
<tokenext>VHDL and Verilog each have their strengths , which is why neither has been able to supplant the other .
Perhaps in the long run System Verilog will change this ( bringing much of the power of VHDL to the Verilog world ) , but that day has n't arrived yet .
  Verilog code tends to be very concise , with the language making some implicit conversions and assumptions that turn out to be correct most of the time .
  VHDL is bigger , bulkier and more rigid .
The rigidity can be annoying , but it also is good at catching errors .
The language has features that allow for very elaborate testbench construction , and some powerful means for abstraction ( the generate statement , multiple architectures for an entity , etc ) .
But this power comes at a cost .
The spec for the language is several times larger than for VHDL .
At one point I had a Verilog quick reference that fit nicely on a single page .
My equivalent quick reference for VHDL covered four pages .
  I 've gone through the " choose an HDL " process twice , and both times selected VHDL .
But that was within the context of at least half the team already being fluent in VHDL , and working on a large enough ( and long lived enough ) codebase that we could take advantage of some of VHDL 's power .
I wish VHDL was n't so cumbersome and verbose , but it was still a win overall .
  You are in a very different situation .
I 'm assuming you have minimal experience with either language , and it will be new to your students as well .
You 're going to have plenty of other things to be worrying about ( digital design , synthesis , debugging , etc ) .
I think Verilog is a better choice for your situation .
It 's going to do everything you need , and not really get in your way .
  Also , do n't worry about which tool is more popular in industry .
Tools change many times over a career .
University classes should be about providing good theory and foundation , so pick whatever tool enables you teach those concepts most effectively .</tokentext>
<sentencetext>VHDL and Verilog each have their strengths, which is why neither has been able to supplant the other.
Perhaps in the long run System Verilog will change this (bringing much of the power of VHDL to the Verilog world), but that day hasn't arrived yet.
  Verilog code tends to be very concise, with the language making some implicit conversions and assumptions that turn out to be correct most of the time.
  VHDL is bigger, bulkier and more rigid.
The rigidity can be annoying, but it also is good at catching errors.
The language has features that allow for very elaborate testbench construction, and some powerful means for abstraction (the generate statement, multiple architectures for an entity, etc).
But this power comes at a cost.
The spec for the language is several times larger than for VHDL.
At one point I had a Verilog quick reference that fit nicely on a single page.
My equivalent quick reference for VHDL covered four pages.
  I've gone through the "choose an HDL" process twice, and both times selected VHDL.
But that was within the context of at least half the team already being fluent in VHDL, and working on a large enough (and long lived enough) codebase that we could take advantage of some of VHDL's power.
I wish VHDL wasn't so cumbersome and verbose, but it was still a win overall.
  You are in a very different situation.
I'm assuming you have minimal experience with either language, and it will be new to your students as well.
You're going to have plenty of other things to be worrying about (digital design, synthesis, debugging, etc).
I think Verilog is a better choice for your situation.
It's going to do everything you need, and not really get in your way.
  Also, don't worry about which tool is more popular in industry.
Tools change many times over a career.
University classes should be about providing good theory and foundation, so pick whatever tool enables you teach those concepts most effectively.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162585</id>
	<title>Give your students the choice</title>
	<author>Anonymous</author>
	<datestamp>1243777140000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Disclaimer: I haven't gone through all the comments but quite a few to get the gist of suggestions</p><p>In school I worked my way on schematics in the first half of the course and was given a choice of learning either of Verilog or VHDL. I learned Verilog more because it was the language of choice in US. But, to tell the truth, people who learnt VHDL were able to translate ideas from schematics to code in a much more efficient way than Verilog.</p><p>I struggled with Verilog for the first couple of months despite having a very strong background in OOPS.. While I did end up making a career in Verilog designs, I still think VHDL is more structured as a language and a far easier transition from schematics to code..</p><p>Verilog though easy to learn will give you a far tougher time if you have a tendency of being a bit less systematic (VHDL forces you to be systematic) - probably more suited for testbench design rather than IC design.... That said Verilog is extremely flexible when implementing multiple threads / pipelines.</p><p>In the end however it boils down to what the students want to learn and different students will have different background in programming. I would probably make VHDL as the suggested choice but keep it open to students to choose Verilog if they are comfortable.</p></htmltext>
<tokenext>Disclaimer : I have n't gone through all the comments but quite a few to get the gist of suggestionsIn school I worked my way on schematics in the first half of the course and was given a choice of learning either of Verilog or VHDL .
I learned Verilog more because it was the language of choice in US .
But , to tell the truth , people who learnt VHDL were able to translate ideas from schematics to code in a much more efficient way than Verilog.I struggled with Verilog for the first couple of months despite having a very strong background in OOPS.. While I did end up making a career in Verilog designs , I still think VHDL is more structured as a language and a far easier transition from schematics to code..Verilog though easy to learn will give you a far tougher time if you have a tendency of being a bit less systematic ( VHDL forces you to be systematic ) - probably more suited for testbench design rather than IC design.... That said Verilog is extremely flexible when implementing multiple threads / pipelines.In the end however it boils down to what the students want to learn and different students will have different background in programming .
I would probably make VHDL as the suggested choice but keep it open to students to choose Verilog if they are comfortable .</tokentext>
<sentencetext>Disclaimer: I haven't gone through all the comments but quite a few to get the gist of suggestionsIn school I worked my way on schematics in the first half of the course and was given a choice of learning either of Verilog or VHDL.
I learned Verilog more because it was the language of choice in US.
But, to tell the truth, people who learnt VHDL were able to translate ideas from schematics to code in a much more efficient way than Verilog.I struggled with Verilog for the first couple of months despite having a very strong background in OOPS.. While I did end up making a career in Verilog designs, I still think VHDL is more structured as a language and a far easier transition from schematics to code..Verilog though easy to learn will give you a far tougher time if you have a tendency of being a bit less systematic (VHDL forces you to be systematic) - probably more suited for testbench design rather than IC design.... That said Verilog is extremely flexible when implementing multiple threads / pipelines.In the end however it boils down to what the students want to learn and different students will have different background in programming.
I would probably make VHDL as the suggested choice but keep it open to students to choose Verilog if they are comfortable.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163333</id>
	<title>Old Notes on VHDL vs Verilog</title>
	<author>Anonymous</author>
	<datestamp>1243783440000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Perspective of Chip Design Industry:<br>http://www.deepchip.com/items/dvcon07-02.html</p><p>The War:<br>http://www.cl.cam.ac.uk/~mjcg/Verilog/Cooley-VHDL-Verilog.html</p><p>The competition:<br>http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html</p><p>I used to design using VHDL. But, the moment I started Verilog, I did not look back again. VHDL is just verbose and counter intuitive.</p></htmltext>
<tokenext>Perspective of Chip Design Industry : http : //www.deepchip.com/items/dvcon07-02.htmlThe War : http : //www.cl.cam.ac.uk/ ~ mjcg/Verilog/Cooley-VHDL-Verilog.htmlThe competition : http : //www.see.ed.ac.uk/ ~ gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.htmlI used to design using VHDL .
But , the moment I started Verilog , I did not look back again .
VHDL is just verbose and counter intuitive .</tokentext>
<sentencetext>Perspective of Chip Design Industry:http://www.deepchip.com/items/dvcon07-02.htmlThe War:http://www.cl.cam.ac.uk/~mjcg/Verilog/Cooley-VHDL-Verilog.htmlThe competition:http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.htmlI used to design using VHDL.
But, the moment I started Verilog, I did not look back again.
VHDL is just verbose and counter intuitive.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161499</id>
	<title>VHDL</title>
	<author>Mister Fright</author>
	<datestamp>1243767300000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I see VHDL mostly used.  I only ever see Verilog in third party libraries or autogenerated code.</p><p>I think language is an individual choice, but whatever you choose, make sure the students actually synthesize something on a chip and try to meet some timing requirements.  Everything works in simulation.</p><p>Also, have them take at least one programming course.  Firmware engineers try to write software as if it were firmware.  Think variables and function names in all caps and absolutely no code reuse.  I'm still fixing this guys terrible code.</p></htmltext>
<tokenext>I see VHDL mostly used .
I only ever see Verilog in third party libraries or autogenerated code.I think language is an individual choice , but whatever you choose , make sure the students actually synthesize something on a chip and try to meet some timing requirements .
Everything works in simulation.Also , have them take at least one programming course .
Firmware engineers try to write software as if it were firmware .
Think variables and function names in all caps and absolutely no code reuse .
I 'm still fixing this guys terrible code .</tokentext>
<sentencetext>I see VHDL mostly used.
I only ever see Verilog in third party libraries or autogenerated code.I think language is an individual choice, but whatever you choose, make sure the students actually synthesize something on a chip and try to meet some timing requirements.
Everything works in simulation.Also, have them take at least one programming course.
Firmware engineers try to write software as if it were firmware.
Think variables and function names in all caps and absolutely no code reuse.
I'm still fixing this guys terrible code.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28175317</id>
	<title>Re:Where are you located?</title>
	<author>yakovlev</author>
	<datestamp>1243857900000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I also agree with this completely.<br><br>I went to a Verilog school and have since moved on to a career with VHDL.  Coming from a mixed hardware/software background, I found it VERY tempting to build something in Verilog that looked pretty to my software design eyes but didn't translate to hardware well at all.  When this happened, I at least understood what was going on and how I had messed up.  For many of my classmates, they had very little concept of how the verilog procedures would be converted into hardware.  There were a lot of class projects where I had to explain: "No, you can't have a procedure like that.  I know it works in C, but in real hardware that is going to be something like 100 stages of logic because you don't have any latch stages in the middle."<br><br>VHDL tends to be built in a way that is much more like real hardware, with the massive concurrency and limited cycle time characteristics being much more obvious.  While it's definitely possible to mess things up, the restrictions of the language tend to make this more clear.</htmltext>
<tokenext>I also agree with this completely.I went to a Verilog school and have since moved on to a career with VHDL .
Coming from a mixed hardware/software background , I found it VERY tempting to build something in Verilog that looked pretty to my software design eyes but did n't translate to hardware well at all .
When this happened , I at least understood what was going on and how I had messed up .
For many of my classmates , they had very little concept of how the verilog procedures would be converted into hardware .
There were a lot of class projects where I had to explain : " No , you ca n't have a procedure like that .
I know it works in C , but in real hardware that is going to be something like 100 stages of logic because you do n't have any latch stages in the middle .
" VHDL tends to be built in a way that is much more like real hardware , with the massive concurrency and limited cycle time characteristics being much more obvious .
While it 's definitely possible to mess things up , the restrictions of the language tend to make this more clear .</tokentext>
<sentencetext>I also agree with this completely.I went to a Verilog school and have since moved on to a career with VHDL.
Coming from a mixed hardware/software background, I found it VERY tempting to build something in Verilog that looked pretty to my software design eyes but didn't translate to hardware well at all.
When this happened, I at least understood what was going on and how I had messed up.
For many of my classmates, they had very little concept of how the verilog procedures would be converted into hardware.
There were a lot of class projects where I had to explain: "No, you can't have a procedure like that.
I know it works in C, but in real hardware that is going to be something like 100 stages of logic because you don't have any latch stages in the middle.
"VHDL tends to be built in a way that is much more like real hardware, with the massive concurrency and limited cycle time characteristics being much more obvious.
While it's definitely possible to mess things up, the restrictions of the language tend to make this more clear.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161653</id>
	<title>Re:Where are you located?</title>
	<author>compgenius3</author>
	<datestamp>1243768560000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I agree entirely, as a student who started with VHDL, I think that it's really easy to switch to Verilog. I find it pretty easy to understand, though the terminology is much harder to understand, as VHDL is more like a natural language. That's just my $0.02</htmltext>
<tokenext>I agree entirely , as a student who started with VHDL , I think that it 's really easy to switch to Verilog .
I find it pretty easy to understand , though the terminology is much harder to understand , as VHDL is more like a natural language .
That 's just my $ 0.02</tokentext>
<sentencetext>I agree entirely, as a student who started with VHDL, I think that it's really easy to switch to Verilog.
I find it pretty easy to understand, though the terminology is much harder to understand, as VHDL is more like a natural language.
That's just my $0.02</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28164519</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243793820000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I would agree with this.  If your student end up using a cutting edge chip once they get out into the real world, I have found that most of the vendor example designs are written in VHDL.</p><p>I found the transition from VHDL to Verilog pretty easy.  Your students will probably learn quite a bit if you teach them VHDL first, throw some Verilog at them in the middle, and maybe a mixed design as extra credit.</p></htmltext>
<tokenext>I would agree with this .
If your student end up using a cutting edge chip once they get out into the real world , I have found that most of the vendor example designs are written in VHDL.I found the transition from VHDL to Verilog pretty easy .
Your students will probably learn quite a bit if you teach them VHDL first , throw some Verilog at them in the middle , and maybe a mixed design as extra credit .</tokentext>
<sentencetext>I would agree with this.
If your student end up using a cutting edge chip once they get out into the real world, I have found that most of the vendor example designs are written in VHDL.I found the transition from VHDL to Verilog pretty easy.
Your students will probably learn quite a bit if you teach them VHDL first, throw some Verilog at them in the middle, and maybe a mixed design as extra credit.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160801</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160887</id>
	<title>(Structural) Verilog</title>
	<author>Roguelazer</author>
	<datestamp>1243761900000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I've found that Verilog is much easier to learn and teach (at least, for an undergraduate engineering-type class). But, as others have mentioned, do NOT think of it as a programming language. Think of it as a convenient way to draw schematics, a very sophisticated keyboard layout for Xilinx. You should ALWAYS write synthesizable code for everything except your testbench, and you shouldn't have to synthesize it to know what it looks like.

As to why not VHDL, well, VHDL is the COBOL of HDLs. Way too verbose for me.</htmltext>
<tokenext>I 've found that Verilog is much easier to learn and teach ( at least , for an undergraduate engineering-type class ) .
But , as others have mentioned , do NOT think of it as a programming language .
Think of it as a convenient way to draw schematics , a very sophisticated keyboard layout for Xilinx .
You should ALWAYS write synthesizable code for everything except your testbench , and you should n't have to synthesize it to know what it looks like .
As to why not VHDL , well , VHDL is the COBOL of HDLs .
Way too verbose for me .</tokentext>
<sentencetext>I've found that Verilog is much easier to learn and teach (at least, for an undergraduate engineering-type class).
But, as others have mentioned, do NOT think of it as a programming language.
Think of it as a convenient way to draw schematics, a very sophisticated keyboard layout for Xilinx.
You should ALWAYS write synthesizable code for everything except your testbench, and you shouldn't have to synthesize it to know what it looks like.
As to why not VHDL, well, VHDL is the COBOL of HDLs.
Way too verbose for me.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160435</id>
	<title>Either</title>
	<author>rosasaul</author>
	<datestamp>1243802220000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>To be honest for a college level program I don't think it matters. I learned VHDL in school, but only use Verilog at work. Hasn't much impeded me. There's a mild learning curve but if you know one you know the concepts necessary to easily learn the other.</htmltext>
<tokenext>To be honest for a college level program I do n't think it matters .
I learned VHDL in school , but only use Verilog at work .
Has n't much impeded me .
There 's a mild learning curve but if you know one you know the concepts necessary to easily learn the other .</tokentext>
<sentencetext>To be honest for a college level program I don't think it matters.
I learned VHDL in school, but only use Verilog at work.
Hasn't much impeded me.
There's a mild learning curve but if you know one you know the concepts necessary to easily learn the other.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160411</id>
	<title>Something completely different...</title>
	<author>Anonymous</author>
	<datestamp>1243802040000</datestamp>
	<modclass>Troll</modclass>
	<modscore>0</modscore>
	<htmltext>Schematic capture is the answer<p>
A picture is worth a thousand words, and a schematic is worth 1,000 lines of VHDL
Disclaimer:</p><p>
I have been using Xilinx since the 1800 (approx 1980).</p></htmltext>
<tokenext>Schematic capture is the answer A picture is worth a thousand words , and a schematic is worth 1,000 lines of VHDL Disclaimer : I have been using Xilinx since the 1800 ( approx 1980 ) .</tokentext>
<sentencetext>Schematic capture is the answer
A picture is worth a thousand words, and a schematic is worth 1,000 lines of VHDL
Disclaimer:
I have been using Xilinx since the 1800 (approx 1980).</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162387</id>
	<title>Verilog for industry</title>
	<author>Anonymous</author>
	<datestamp>1243775220000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>As a Computer Enginnering Graduate, with experience in VHDL (coded 32-bit RISC based microprocessor), I would say go for Verilog.<br>For one, the industry for which students need to be prepared, is using Verilog( I interviewed for Nvidia and they asked for Verilog, though they would "let" you code in VHDL).<br>For another, since you say you're aware of C/C++, the syntax is somewhat similar, easing the learning curve,<br>Hope, this helps,<br>Shubham Harnal.</p></htmltext>
<tokenext>As a Computer Enginnering Graduate , with experience in VHDL ( coded 32-bit RISC based microprocessor ) , I would say go for Verilog.For one , the industry for which students need to be prepared , is using Verilog ( I interviewed for Nvidia and they asked for Verilog , though they would " let " you code in VHDL ) .For another , since you say you 're aware of C/C + + , the syntax is somewhat similar , easing the learning curve,Hope , this helps,Shubham Harnal .</tokentext>
<sentencetext>As a Computer Enginnering Graduate, with experience in VHDL (coded 32-bit RISC based microprocessor), I would say go for Verilog.For one, the industry for which students need to be prepared, is using Verilog( I interviewed for Nvidia and they asked for Verilog, though they would "let" you code in VHDL).For another, since you say you're aware of C/C++, the syntax is somewhat similar, easing the learning curve,Hope, this helps,Shubham Harnal.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163269</id>
	<title>Missing option: AHDL</title>
	<author>tippe</author>
	<datestamp>1243782840000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>I kid, I kid.  Does anyone still use that language? FYI: AHDL was (is?) a proprietary HDL language designed by Altera for use with their FPGA.  I had to modify a design that used it once.  It was aweful.  I'm glad I've never had to use it again...</p><p>Anyway, I don't think it really matters what language you use to teach.  According to the summary, this is a university (i.e. higher education) course, not some college training course.  Teaching the proper hardware (ASIC, FPGA, whatever) design concepts should be your real challenge; what language you use to convey those concepts, to illustrate examples with, and require students to use in their assignments, projects and exams is (I would say) incidental.  Maybe you should teach both, or hell, maybe you should teach only in AHDL and then require that your students use only VHDL or verilog for their assignments and projects (just kidding; that would be really evil).</p><p>In university, my work-terms, and for the first 4 years of my career, I only worked only in VHDL (and very briefly in AHDL), as that was the language my school and employers used (I'm in Waterloo ON, which appears to have sided with the US east coast, which traditionally has been VHDL).  6 yrs ago I started work at another company that used only verilog.  Becoming proficient at writing verilog from scratch took a little while (a week or two, tops), but understanding (the gist of) designs written in verilog took no time at all.  In the grand scheme of things, learning a new language if you already have a solid understanding of underlying design concepts is practically zero cost.  All you need to make a quick transition is a decent reference book (or the internet) to look up syntax and concepts, a deliverable, and a looming deadline to get you motivated.  That's all I needed, anyway; I certainly didn't need to take any verilog courses.  I would almost say that it's a much bigger conceptual jump to move from coding for FPGAs to coding for ASICs then it is to jump from VHDL to verilog or vice versa.</p><p>So, personally, I would say that you shouldn't worry too much about the language, as that shouldn't be the primary focus of your course.  It's definitely a required component to your course, but not the primary one.  Concepts such as concurrent vs. sequential (processes), component inference vs instantiation, blocking vs non-blocking assignments, sequential vs combinatorial logic, zero-delay vs timing annotated simulation, synthesizable vs non-synthesizable logic, and a crap load of other digital design, simulation, synthesis, etc concepts are relevant in both languages and must be well understood before you can really be successful at designing with either of them.</p></htmltext>
<tokenext>I kid , I kid .
Does anyone still use that language ?
FYI : AHDL was ( is ?
) a proprietary HDL language designed by Altera for use with their FPGA .
I had to modify a design that used it once .
It was aweful .
I 'm glad I 've never had to use it again...Anyway , I do n't think it really matters what language you use to teach .
According to the summary , this is a university ( i.e .
higher education ) course , not some college training course .
Teaching the proper hardware ( ASIC , FPGA , whatever ) design concepts should be your real challenge ; what language you use to convey those concepts , to illustrate examples with , and require students to use in their assignments , projects and exams is ( I would say ) incidental .
Maybe you should teach both , or hell , maybe you should teach only in AHDL and then require that your students use only VHDL or verilog for their assignments and projects ( just kidding ; that would be really evil ) .In university , my work-terms , and for the first 4 years of my career , I only worked only in VHDL ( and very briefly in AHDL ) , as that was the language my school and employers used ( I 'm in Waterloo ON , which appears to have sided with the US east coast , which traditionally has been VHDL ) .
6 yrs ago I started work at another company that used only verilog .
Becoming proficient at writing verilog from scratch took a little while ( a week or two , tops ) , but understanding ( the gist of ) designs written in verilog took no time at all .
In the grand scheme of things , learning a new language if you already have a solid understanding of underlying design concepts is practically zero cost .
All you need to make a quick transition is a decent reference book ( or the internet ) to look up syntax and concepts , a deliverable , and a looming deadline to get you motivated .
That 's all I needed , anyway ; I certainly did n't need to take any verilog courses .
I would almost say that it 's a much bigger conceptual jump to move from coding for FPGAs to coding for ASICs then it is to jump from VHDL to verilog or vice versa.So , personally , I would say that you should n't worry too much about the language , as that should n't be the primary focus of your course .
It 's definitely a required component to your course , but not the primary one .
Concepts such as concurrent vs. sequential ( processes ) , component inference vs instantiation , blocking vs non-blocking assignments , sequential vs combinatorial logic , zero-delay vs timing annotated simulation , synthesizable vs non-synthesizable logic , and a crap load of other digital design , simulation , synthesis , etc concepts are relevant in both languages and must be well understood before you can really be successful at designing with either of them .</tokentext>
<sentencetext>I kid, I kid.
Does anyone still use that language?
FYI: AHDL was (is?
) a proprietary HDL language designed by Altera for use with their FPGA.
I had to modify a design that used it once.
It was aweful.
I'm glad I've never had to use it again...Anyway, I don't think it really matters what language you use to teach.
According to the summary, this is a university (i.e.
higher education) course, not some college training course.
Teaching the proper hardware (ASIC, FPGA, whatever) design concepts should be your real challenge; what language you use to convey those concepts, to illustrate examples with, and require students to use in their assignments, projects and exams is (I would say) incidental.
Maybe you should teach both, or hell, maybe you should teach only in AHDL and then require that your students use only VHDL or verilog for their assignments and projects (just kidding; that would be really evil).In university, my work-terms, and for the first 4 years of my career, I only worked only in VHDL (and very briefly in AHDL), as that was the language my school and employers used (I'm in Waterloo ON, which appears to have sided with the US east coast, which traditionally has been VHDL).
6 yrs ago I started work at another company that used only verilog.
Becoming proficient at writing verilog from scratch took a little while (a week or two, tops), but understanding (the gist of) designs written in verilog took no time at all.
In the grand scheme of things, learning a new language if you already have a solid understanding of underlying design concepts is practically zero cost.
All you need to make a quick transition is a decent reference book (or the internet) to look up syntax and concepts, a deliverable, and a looming deadline to get you motivated.
That's all I needed, anyway; I certainly didn't need to take any verilog courses.
I would almost say that it's a much bigger conceptual jump to move from coding for FPGAs to coding for ASICs then it is to jump from VHDL to verilog or vice versa.So, personally, I would say that you shouldn't worry too much about the language, as that shouldn't be the primary focus of your course.
It's definitely a required component to your course, but not the primary one.
Concepts such as concurrent vs. sequential (processes), component inference vs instantiation, blocking vs non-blocking assignments, sequential vs combinatorial logic, zero-delay vs timing annotated simulation, synthesizable vs non-synthesizable logic, and a crap load of other digital design, simulation, synthesis, etc concepts are relevant in both languages and must be well understood before you can really be successful at designing with either of them.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161975</id>
	<title>I just did such a course..</title>
	<author>Goseph</author>
	<datestamp>1243771680000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I'm an undergraduate student and just finished a course in VHDL implemented on the Xilinx Spartan3-series FPGA and found it highly enjoyable. Definitely don't attempt to cram both in one module as I have no doubt that would confuse the kids no end. Instead get them comfortable with one and take that a bit further. I found Verilog a bit less intuitive but I did spend less time studying it.</htmltext>
<tokenext>I 'm an undergraduate student and just finished a course in VHDL implemented on the Xilinx Spartan3-series FPGA and found it highly enjoyable .
Definitely do n't attempt to cram both in one module as I have no doubt that would confuse the kids no end .
Instead get them comfortable with one and take that a bit further .
I found Verilog a bit less intuitive but I did spend less time studying it .</tokentext>
<sentencetext>I'm an undergraduate student and just finished a course in VHDL implemented on the Xilinx Spartan3-series FPGA and found it highly enjoyable.
Definitely don't attempt to cram both in one module as I have no doubt that would confuse the kids no end.
Instead get them comfortable with one and take that a bit further.
I found Verilog a bit less intuitive but I did spend less time studying it.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163963</id>
	<title>Re:Where are you located?</title>
	<author>k8to</author>
	<datestamp>1243788540000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>um, no.</p><p>When you author things in programming languages, you get... a program.</p><p>What you are designing in HDL is hardware.</p><p>There's some overlap.  Stuff like algorithms may be used in both arenas, but the goal of HDL is to make hardware, not programs.</p></htmltext>
<tokenext>um , no.When you author things in programming languages , you get... a program.What you are designing in HDL is hardware.There 's some overlap .
Stuff like algorithms may be used in both arenas , but the goal of HDL is to make hardware , not programs .</tokentext>
<sentencetext>um, no.When you author things in programming languages, you get... a program.What you are designing in HDL is hardware.There's some overlap.
Stuff like algorithms may be used in both arenas, but the goal of HDL is to make hardware, not programs.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161697</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162031</id>
	<title>First ever slashdot contribution</title>
	<author>TwoWheelGeek</author>
	<datestamp>1243772100000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext>Finally a topic I care enough to go register in order to put in my opinion... Let's see how bad I get slammed<nobr> <wbr></nobr>:)
I work in FPGA's and have done a couple of relatively small projects in them.  I have exclusively used VHDL.  But after I taught myself VHDL, reading Verilog is pretty easy.

It is a Coke / Pepsi thing because you are asking for a "better" decision.  Most jobs can be done by either language.  VHDL is preferred in some circles, especially military / DOD / Aerospace (where I work).

Verilog has a shallower learning curve for those used to sequential programming languages like C.

VHDL is more powerful if you can think in terms of the underlying digital hardware (propagation delays, clock hold times, clock domains, etc).

And not to be too pedantic, but VHDL is NOT a programming language.  A programming language is something that ultimately is translated into a series of instructions for a processor.  VHDL is a hardware description language.  You are actually describing a piece of hardware that will be implemented as a set of gates on a piece of silicon.  VHDL code will never result in instructions and will never be "ran".  It will be implemented in hardware and will respond to inputs and produce outputs per your design.

My answer, it depends on your goal.  If you want to produce a more rounded CS major capable of understanding this aspect of technology, focus on teaching Verilog with some VHDL examples to highlight the differences.  If you want someone that could go produce useful work after graduation, focus on VHDL.

I know I will probably be unpopular because Verilog is more prevalent among the "traditional" programmers because it is an easier leap from C.</htmltext>
<tokenext>Finally a topic I care enough to go register in order to put in my opinion... Let 's see how bad I get slammed : ) I work in FPGA 's and have done a couple of relatively small projects in them .
I have exclusively used VHDL .
But after I taught myself VHDL , reading Verilog is pretty easy .
It is a Coke / Pepsi thing because you are asking for a " better " decision .
Most jobs can be done by either language .
VHDL is preferred in some circles , especially military / DOD / Aerospace ( where I work ) .
Verilog has a shallower learning curve for those used to sequential programming languages like C . VHDL is more powerful if you can think in terms of the underlying digital hardware ( propagation delays , clock hold times , clock domains , etc ) .
And not to be too pedantic , but VHDL is NOT a programming language .
A programming language is something that ultimately is translated into a series of instructions for a processor .
VHDL is a hardware description language .
You are actually describing a piece of hardware that will be implemented as a set of gates on a piece of silicon .
VHDL code will never result in instructions and will never be " ran " .
It will be implemented in hardware and will respond to inputs and produce outputs per your design .
My answer , it depends on your goal .
If you want to produce a more rounded CS major capable of understanding this aspect of technology , focus on teaching Verilog with some VHDL examples to highlight the differences .
If you want someone that could go produce useful work after graduation , focus on VHDL .
I know I will probably be unpopular because Verilog is more prevalent among the " traditional " programmers because it is an easier leap from C .</tokentext>
<sentencetext>Finally a topic I care enough to go register in order to put in my opinion... Let's see how bad I get slammed :)
I work in FPGA's and have done a couple of relatively small projects in them.
I have exclusively used VHDL.
But after I taught myself VHDL, reading Verilog is pretty easy.
It is a Coke / Pepsi thing because you are asking for a "better" decision.
Most jobs can be done by either language.
VHDL is preferred in some circles, especially military / DOD / Aerospace (where I work).
Verilog has a shallower learning curve for those used to sequential programming languages like C.

VHDL is more powerful if you can think in terms of the underlying digital hardware (propagation delays, clock hold times, clock domains, etc).
And not to be too pedantic, but VHDL is NOT a programming language.
A programming language is something that ultimately is translated into a series of instructions for a processor.
VHDL is a hardware description language.
You are actually describing a piece of hardware that will be implemented as a set of gates on a piece of silicon.
VHDL code will never result in instructions and will never be "ran".
It will be implemented in hardware and will respond to inputs and produce outputs per your design.
My answer, it depends on your goal.
If you want to produce a more rounded CS major capable of understanding this aspect of technology, focus on teaching Verilog with some VHDL examples to highlight the differences.
If you want someone that could go produce useful work after graduation, focus on VHDL.
I know I will probably be unpopular because Verilog is more prevalent among the "traditional" programmers because it is an easier leap from C.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163589</id>
	<title>What about Labview?</title>
	<author>Anonymous</author>
	<datestamp>1243785180000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Labview has extensive graphical programming capabilities for their data acquisition boards; however, I don't know how easy it is to use their software for FPGA programming.</p></htmltext>
<tokenext>Labview has extensive graphical programming capabilities for their data acquisition boards ; however , I do n't know how easy it is to use their software for FPGA programming .</tokentext>
<sentencetext>Labview has extensive graphical programming capabilities for their data acquisition boards; however, I don't know how easy it is to use their software for FPGA programming.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165029</id>
	<title>As a current undergrad I choose Verilog</title>
	<author>Anonymous</author>
	<datestamp>1243886760000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>I am an undergraduate student at the University of Colorado and I can tell you that we use Verilog here.  Verilog was easy to pick up while I find VHDL more difficult.</p></htmltext>
<tokenext>I am an undergraduate student at the University of Colorado and I can tell you that we use Verilog here .
Verilog was easy to pick up while I find VHDL more difficult .</tokentext>
<sentencetext>I am an undergraduate student at the University of Colorado and I can tell you that we use Verilog here.
Verilog was easy to pick up while I find VHDL more difficult.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162195</id>
	<title>THUD</title>
	<author>10am-bedtime</author>
	<datestamp>1243773660000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p> Time to shamelessly (neither VHDL nor Verilog) plug
<a href="http://www.gnuvola.org/software/thud/" title="gnuvola.org">THUD</a> [gnuvola.org].
If you are a fan of parentheses (there is an "emacs" tag, above, after all),
just imagine your LFSR components nicely
<a href="http://www.gnuvola.org/software/j/mic-paren/" title="gnuvola.org">bolded</a> [gnuvola.org]
and
<a href="http://www.gnu.org/software/emacs/" title="gnu.org">stuff</a> [gnu.org]....</p></htmltext>
<tokenext>Time to shamelessly ( neither VHDL nor Verilog ) plug THUD [ gnuvola.org ] .
If you are a fan of parentheses ( there is an " emacs " tag , above , after all ) , just imagine your LFSR components nicely bolded [ gnuvola.org ] and stuff [ gnu.org ] ... .</tokentext>
<sentencetext> Time to shamelessly (neither VHDL nor Verilog) plug
THUD [gnuvola.org].
If you are a fan of parentheses (there is an "emacs" tag, above, after all),
just imagine your LFSR components nicely
bolded [gnuvola.org]
and
stuff [gnu.org]....</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28164891</id>
	<title>Just Remember...  Simulation /= Sythesis</title>
	<author>TooManyNames</author>
	<datestamp>1243798500000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>It doesn't really matter whether you choose VHDL or Verilog as long as you know what your synthesis tools are doing.  Both languages are very different from C or other compiled languages in that C allows you to assume that statements will occur sequentially (and yes I know that statements may be re-ordered behind the scenes such that they don't break dependencies) whereas neither HDL will give you that guarantee.  In fact, unless explicitly stated, HDL statements will all execute concurrently (and certainly won't wait for something like a clock edge).
<br> <br>
Now here comes the important part.  You can write VHDL or Verilog such that your design will simulate perfectly (even without using simulation-only constraints like after statements in VHDL) but fail miserably when synthesized for an FPGA.  In my experiences, this has almost always resulted from latches being inferred by the synthesis tools.  This is where you need to know a little information specific to FPGAs; namely, code using latches offers no benefits over code using flip-flops when dealing with FPGAs.  Much of the time, synthesis tools will just set up a combinational loop in the hopes that such latches will act as a they should (they usually won't) because most of the basic blocks that comprise an FPGA utilize flip-flops, not latches.
<br> <br>
If you're interested in a good source describing how to write VHDL for FPGAs, I'd suggest looking at Jiri Gaisler's method:
<a href="http://www.gaisler.com/doc/vhdl2proc.pdf" title="gaisler.com" rel="nofollow">http://www.gaisler.com/doc/vhdl2proc.pdf</a> [gaisler.com]
<br> <br>
Also, avoid statements like:
if clk'event and clk = '1' then<nobr> <wbr></nobr>.... end if;
when statements like:
if rising\_edge(clk) then<nobr> <wbr></nobr>.... end if;
work just fine (and are more readable).</htmltext>
<tokenext>It does n't really matter whether you choose VHDL or Verilog as long as you know what your synthesis tools are doing .
Both languages are very different from C or other compiled languages in that C allows you to assume that statements will occur sequentially ( and yes I know that statements may be re-ordered behind the scenes such that they do n't break dependencies ) whereas neither HDL will give you that guarantee .
In fact , unless explicitly stated , HDL statements will all execute concurrently ( and certainly wo n't wait for something like a clock edge ) .
Now here comes the important part .
You can write VHDL or Verilog such that your design will simulate perfectly ( even without using simulation-only constraints like after statements in VHDL ) but fail miserably when synthesized for an FPGA .
In my experiences , this has almost always resulted from latches being inferred by the synthesis tools .
This is where you need to know a little information specific to FPGAs ; namely , code using latches offers no benefits over code using flip-flops when dealing with FPGAs .
Much of the time , synthesis tools will just set up a combinational loop in the hopes that such latches will act as a they should ( they usually wo n't ) because most of the basic blocks that comprise an FPGA utilize flip-flops , not latches .
If you 're interested in a good source describing how to write VHDL for FPGAs , I 'd suggest looking at Jiri Gaisler 's method : http : //www.gaisler.com/doc/vhdl2proc.pdf [ gaisler.com ] Also , avoid statements like : if clk'event and clk = '1 ' then .... end if ; when statements like : if rising \ _edge ( clk ) then .... end if ; work just fine ( and are more readable ) .</tokentext>
<sentencetext>It doesn't really matter whether you choose VHDL or Verilog as long as you know what your synthesis tools are doing.
Both languages are very different from C or other compiled languages in that C allows you to assume that statements will occur sequentially (and yes I know that statements may be re-ordered behind the scenes such that they don't break dependencies) whereas neither HDL will give you that guarantee.
In fact, unless explicitly stated, HDL statements will all execute concurrently (and certainly won't wait for something like a clock edge).
Now here comes the important part.
You can write VHDL or Verilog such that your design will simulate perfectly (even without using simulation-only constraints like after statements in VHDL) but fail miserably when synthesized for an FPGA.
In my experiences, this has almost always resulted from latches being inferred by the synthesis tools.
This is where you need to know a little information specific to FPGAs; namely, code using latches offers no benefits over code using flip-flops when dealing with FPGAs.
Much of the time, synthesis tools will just set up a combinational loop in the hopes that such latches will act as a they should (they usually won't) because most of the basic blocks that comprise an FPGA utilize flip-flops, not latches.
If you're interested in a good source describing how to write VHDL for FPGAs, I'd suggest looking at Jiri Gaisler's method:
http://www.gaisler.com/doc/vhdl2proc.pdf [gaisler.com]
 
Also, avoid statements like:
if clk'event and clk = '1' then .... end if;
when statements like:
if rising\_edge(clk) then .... end if;
work just fine (and are more readable).</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161227</id>
	<title>What holy war?</title>
	<author>loufoque</author>
	<datestamp>1243764840000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><blockquote><div><p>Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?)</p></div></blockquote><p>I don't see any holy war here.<br>Nvidia (only one that cares about OpenGL), Intel (Core 2 basically killed AMD), and Coke (has 15\% more market share).</p></div>
	</htmltext>
<tokenext>Or is this an eternal , undecidable holy-war question along the lines of ATI/nVidia , AMD/Intel , Coke/Pepsi , etc... ?
) I do n't see any holy war here.Nvidia ( only one that cares about OpenGL ) , Intel ( Core 2 basically killed AMD ) , and Coke ( has 15 \ % more market share ) .</tokentext>
<sentencetext>Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?
)I don't see any holy war here.Nvidia (only one that cares about OpenGL), Intel (Core 2 basically killed AMD), and Coke (has 15\% more market share).
	</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160537</id>
	<title>how about this approach</title>
	<author>Dolphinzilla</author>
	<datestamp>1243802940000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Personally we usually look for VHDL programmers instead of verilog - I would recommend focusing primarily on VHDL, touch on Verilog AND maybe expose the students to LabVIEW for FPGA's, or possibly Annapolis Micro's Corefire software just to show them that there are other approaches besides VHDL and Verilog</p></htmltext>
<tokenext>Personally we usually look for VHDL programmers instead of verilog - I would recommend focusing primarily on VHDL , touch on Verilog AND maybe expose the students to LabVIEW for FPGA 's , or possibly Annapolis Micro 's Corefire software just to show them that there are other approaches besides VHDL and Verilog</tokentext>
<sentencetext>Personally we usually look for VHDL programmers instead of verilog - I would recommend focusing primarily on VHDL, touch on Verilog AND maybe expose the students to LabVIEW for FPGA's, or possibly Annapolis Micro's Corefire software just to show them that there are other approaches besides VHDL and Verilog</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165067</id>
	<title>VHDL IDE</title>
	<author>Anonymous</author>
	<datestamp>1243887840000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>This is indeed an eternal, undecidable holy-war question...</p><p>I vote for VHDL. Recently <a href="http://www.sigasi.com/" title="sigasi.com" rel="nofollow">Sigasi</a> [sigasi.com] released an <a href="http://www.edadesignline.com/news/217600138" title="edadesignline.com" rel="nofollow">Intelligent Development Environment</a> [edadesignline.com] for VHDL which relieves VHDL's verbosity and heavy syntax. This IDE is very similar to Eclipse and Visual Studio. It even has <a href="http://en.wikipedia.org/wiki/Code\_refactoring#Hardware\_refactoring" title="wikipedia.org" rel="nofollow">hardware refactoring</a> [wikipedia.org] support.</p></htmltext>
<tokenext>This is indeed an eternal , undecidable holy-war question...I vote for VHDL .
Recently Sigasi [ sigasi.com ] released an Intelligent Development Environment [ edadesignline.com ] for VHDL which relieves VHDL 's verbosity and heavy syntax .
This IDE is very similar to Eclipse and Visual Studio .
It even has hardware refactoring [ wikipedia.org ] support .</tokentext>
<sentencetext>This is indeed an eternal, undecidable holy-war question...I vote for VHDL.
Recently Sigasi [sigasi.com] released an Intelligent Development Environment [edadesignline.com] for VHDL which relieves VHDL's verbosity and heavy syntax.
This IDE is very similar to Eclipse and Visual Studio.
It even has hardware refactoring [wikipedia.org] support.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163771</id>
	<title>Re:Where are you located?</title>
	<author>Lucky75</author>
	<datestamp>1243786560000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>I'd have to say VHDL based solely on the fact that it's the one I'm more used to using. There's a reason why most university's teach VHDL...</htmltext>
<tokenext>I 'd have to say VHDL based solely on the fact that it 's the one I 'm more used to using .
There 's a reason why most university 's teach VHDL.. .</tokentext>
<sentencetext>I'd have to say VHDL based solely on the fact that it's the one I'm more used to using.
There's a reason why most university's teach VHDL...</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159981</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161007</id>
	<title>FPGA SDK's for Student's to work on...</title>
	<author>file\_reaper</author>
	<datestamp>1243762800000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>This might be offtopic, but while we're on the topic here, does anyone know of any *afforable* FPGA kits for students?</p><p>Our university used the Altera DE2 boards, found here <a href="http://users.ece.gatech.edu/~hamblen/DE2/" title="gatech.edu" rel="nofollow">http://users.ece.gatech.edu/~hamblen/DE2/</a> [gatech.edu]</p><p>I really liked the DE2 because it has a whole lot of peripherals and can be used with Quartus II. I wanted to get one so I could tinker with it in my own time for fun.</p><p>Any recommendations for one less than $500~ ?</p></htmltext>
<tokenext>This might be offtopic , but while we 're on the topic here , does anyone know of any * afforable * FPGA kits for students ? Our university used the Altera DE2 boards , found here http : //users.ece.gatech.edu/ ~ hamblen/DE2/ [ gatech.edu ] I really liked the DE2 because it has a whole lot of peripherals and can be used with Quartus II .
I wanted to get one so I could tinker with it in my own time for fun.Any recommendations for one less than $ 500 ~ ?</tokentext>
<sentencetext>This might be offtopic, but while we're on the topic here, does anyone know of any *afforable* FPGA kits for students?Our university used the Altera DE2 boards, found here http://users.ece.gatech.edu/~hamblen/DE2/ [gatech.edu]I really liked the DE2 because it has a whole lot of peripherals and can be used with Quartus II.
I wanted to get one so I could tinker with it in my own time for fun.Any recommendations for one less than $500~ ?</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28167039</id>
	<title>The answer is both</title>
	<author>imgod2u</author>
	<datestamp>1243866660000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>It's like asking "C++ or Java?". It's not important. What is important is to understand the digital design concepts. Once you've gotten that down, the syntax you need to know in order to design synthesizable circuits in either language is actually quite trivial to learn.</p><p>I think Verilog is a cleaner language myself. ASIC designers generally use Verilog whereas VHDL seems to be more dominant in Defense and government designs.</p><p>Most good design books will provide both VHDL and Verilog examples. I would highly recommend "HDL Chip Design" by Douglas Smith. It's no longer in print -- and the used ones still sell for ~$200 -- but it is probably the best book on the topic you'll find.</p></htmltext>
<tokenext>It 's like asking " C + + or Java ? " .
It 's not important .
What is important is to understand the digital design concepts .
Once you 've gotten that down , the syntax you need to know in order to design synthesizable circuits in either language is actually quite trivial to learn.I think Verilog is a cleaner language myself .
ASIC designers generally use Verilog whereas VHDL seems to be more dominant in Defense and government designs.Most good design books will provide both VHDL and Verilog examples .
I would highly recommend " HDL Chip Design " by Douglas Smith .
It 's no longer in print -- and the used ones still sell for ~ $ 200 -- but it is probably the best book on the topic you 'll find .</tokentext>
<sentencetext>It's like asking "C++ or Java?".
It's not important.
What is important is to understand the digital design concepts.
Once you've gotten that down, the syntax you need to know in order to design synthesizable circuits in either language is actually quite trivial to learn.I think Verilog is a cleaner language myself.
ASIC designers generally use Verilog whereas VHDL seems to be more dominant in Defense and government designs.Most good design books will provide both VHDL and Verilog examples.
I would highly recommend "HDL Chip Design" by Douglas Smith.
It's no longer in print -- and the used ones still sell for ~$200 -- but it is probably the best book on the topic you'll find.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160811</id>
	<title>Verilog 100\% No Question</title>
	<author>Anonymous</author>
	<datestamp>1243761480000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>1</modscore>
	<htmltext>Verilog, I've had to program FPGA's and CPLD's and the one thing I can say for sure is VHDL is the worst programming lanugange of all time.  It's syntax is horrible, it's keywords are non sense, it's declerations are crap, all in all it's horrible.
<br>
<br>
Vhdl solves 0 problems with helping a student learn hardware design.  From a personal note I don't think anyone should use FPGA's / CPLD's.  They don't solve a single problem that can't be done in pure software.  Future more what use is it to say make a Train program on a FPGA / CPLD.   There is real use for these hardware device.
<br>
<br>
My prof made it sound like they were the most important devices in the world and I have to disagree with him completely.  I would understand 5 - 10 years ago when we simply didn't have the hardware preformance we have now, then a FPGA / CPLD could be useful.
<br>
<br>
Well VHDL might have a ton of existing libs for it and it might be reconized widely, it's still a horrible and hidious method of hardware design period.  We had to do many labs this year using it and really there was no time saved, NONE, and from what we were taught it would make the job easiler!
<br>
<br>
After spending 4 months with VHDL and then 1 week with Verilog, there's no completion.  Verilog is a much much better method of programming FPGA's / CPLD's.  Hands down it wins, it's like asking which is better for programming a airport system , Hand Assembling the software using ATT&amp;T syntax in Windows Debug (VHDL) or using C (Verilog).   All the labs the entire class did were preformed 1000x faster in Verilog with a much higher level of understanding.
<br>
<br>
If you have to pick, it's not a question just and answer it's Verilog all the way.  VHDL has to retire, it's of no use, it's horrible to work with, it's horrible to use and forget trying to understand it to a decent level.   Verilog is very nice to work with and it omits many of the down falls of VHDL.
<br>
<br>
I would also like to add that doing FPGA / CPLD design is also becoming rather pointless, with the advances in modern computer programming languages and compiler, it's no longer a case of not having a fast software solution.  The hardware and the software are no longer seperated by such a huge amount, well there might be a slight and I mean maybe 1 - 5\% increase in preformance using a FPGA / CPLD I don't think that becomes enough of a reason for using them anymore.   At least not in college and university programs, doing labs where you have to program a game like Tetris or Space Invaders, what does that teach you.   What it does is waste hours and hours of dealing with problems and bugs and crappy syntax do get something that doesn't satify any need.
<br>
<br>
All in all I think the FPGA and the CPLD,except in special cases, have served there purpose and are no longer a good solution to computer and electronic design.   Unless someone can make a hardware desciption language that can actually make sense and flow, the FPGA and CPLD's are done.
<br>
<br>
Thanks
<br>
Murdoch</htmltext>
<tokenext>Verilog , I 've had to program FPGA 's and CPLD 's and the one thing I can say for sure is VHDL is the worst programming lanugange of all time .
It 's syntax is horrible , it 's keywords are non sense , it 's declerations are crap , all in all it 's horrible .
Vhdl solves 0 problems with helping a student learn hardware design .
From a personal note I do n't think anyone should use FPGA 's / CPLD 's .
They do n't solve a single problem that ca n't be done in pure software .
Future more what use is it to say make a Train program on a FPGA / CPLD .
There is real use for these hardware device .
My prof made it sound like they were the most important devices in the world and I have to disagree with him completely .
I would understand 5 - 10 years ago when we simply did n't have the hardware preformance we have now , then a FPGA / CPLD could be useful .
Well VHDL might have a ton of existing libs for it and it might be reconized widely , it 's still a horrible and hidious method of hardware design period .
We had to do many labs this year using it and really there was no time saved , NONE , and from what we were taught it would make the job easiler !
After spending 4 months with VHDL and then 1 week with Verilog , there 's no completion .
Verilog is a much much better method of programming FPGA 's / CPLD 's .
Hands down it wins , it 's like asking which is better for programming a airport system , Hand Assembling the software using ATT&amp;T syntax in Windows Debug ( VHDL ) or using C ( Verilog ) .
All the labs the entire class did were preformed 1000x faster in Verilog with a much higher level of understanding .
If you have to pick , it 's not a question just and answer it 's Verilog all the way .
VHDL has to retire , it 's of no use , it 's horrible to work with , it 's horrible to use and forget trying to understand it to a decent level .
Verilog is very nice to work with and it omits many of the down falls of VHDL .
I would also like to add that doing FPGA / CPLD design is also becoming rather pointless , with the advances in modern computer programming languages and compiler , it 's no longer a case of not having a fast software solution .
The hardware and the software are no longer seperated by such a huge amount , well there might be a slight and I mean maybe 1 - 5 \ % increase in preformance using a FPGA / CPLD I do n't think that becomes enough of a reason for using them anymore .
At least not in college and university programs , doing labs where you have to program a game like Tetris or Space Invaders , what does that teach you .
What it does is waste hours and hours of dealing with problems and bugs and crappy syntax do get something that does n't satify any need .
All in all I think the FPGA and the CPLD,except in special cases , have served there purpose and are no longer a good solution to computer and electronic design .
Unless someone can make a hardware desciption language that can actually make sense and flow , the FPGA and CPLD 's are done .
Thanks Murdoch</tokentext>
<sentencetext>Verilog, I've had to program FPGA's and CPLD's and the one thing I can say for sure is VHDL is the worst programming lanugange of all time.
It's syntax is horrible, it's keywords are non sense, it's declerations are crap, all in all it's horrible.
Vhdl solves 0 problems with helping a student learn hardware design.
From a personal note I don't think anyone should use FPGA's / CPLD's.
They don't solve a single problem that can't be done in pure software.
Future more what use is it to say make a Train program on a FPGA / CPLD.
There is real use for these hardware device.
My prof made it sound like they were the most important devices in the world and I have to disagree with him completely.
I would understand 5 - 10 years ago when we simply didn't have the hardware preformance we have now, then a FPGA / CPLD could be useful.
Well VHDL might have a ton of existing libs for it and it might be reconized widely, it's still a horrible and hidious method of hardware design period.
We had to do many labs this year using it and really there was no time saved, NONE, and from what we were taught it would make the job easiler!
After spending 4 months with VHDL and then 1 week with Verilog, there's no completion.
Verilog is a much much better method of programming FPGA's / CPLD's.
Hands down it wins, it's like asking which is better for programming a airport system , Hand Assembling the software using ATT&amp;T syntax in Windows Debug (VHDL) or using C (Verilog).
All the labs the entire class did were preformed 1000x faster in Verilog with a much higher level of understanding.
If you have to pick, it's not a question just and answer it's Verilog all the way.
VHDL has to retire, it's of no use, it's horrible to work with, it's horrible to use and forget trying to understand it to a decent level.
Verilog is very nice to work with and it omits many of the down falls of VHDL.
I would also like to add that doing FPGA / CPLD design is also becoming rather pointless, with the advances in modern computer programming languages and compiler, it's no longer a case of not having a fast software solution.
The hardware and the software are no longer seperated by such a huge amount, well there might be a slight and I mean maybe 1 - 5\% increase in preformance using a FPGA / CPLD I don't think that becomes enough of a reason for using them anymore.
At least not in college and university programs, doing labs where you have to program a game like Tetris or Space Invaders, what does that teach you.
What it does is waste hours and hours of dealing with problems and bugs and crappy syntax do get something that doesn't satify any need.
All in all I think the FPGA and the CPLD,except in special cases, have served there purpose and are no longer a good solution to computer and electronic design.
Unless someone can make a hardware desciption language that can actually make sense and flow, the FPGA and CPLD's are done.
Thanks

Murdoch</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161697</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243769040000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>1</modscore>
	<htmltext><blockquote><div><p>"2) Thinking of Verilog as a programming language at all. HDL stands for "Hardware description language," and that's what they are.</p></div></blockquote><p> <b> <i>BZZZT</i></b> You agree VHDL is a language.  Do you plan on speaking it, or using it to program?  It might be a huge mistake to compare it closely with C or C++, but is is <b> <i>absolutely</i> </b> a programming language.</p></div>
	</htmltext>
<tokenext>" 2 ) Thinking of Verilog as a programming language at all .
HDL stands for " Hardware description language , " and that 's what they are .
BZZZT You agree VHDL is a language .
Do you plan on speaking it , or using it to program ?
It might be a huge mistake to compare it closely with C or C + + , but is is absolutely a programming language .</tokentext>
<sentencetext>"2) Thinking of Verilog as a programming language at all.
HDL stands for "Hardware description language," and that's what they are.
BZZZT You agree VHDL is a language.
Do you plan on speaking it, or using it to program?
It might be a huge mistake to compare it closely with C or C++, but is is  absolutely  a programming language.
	</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160131</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163515</id>
	<title>Icarus Verilog - Open Source  Simulator</title>
	<author>Anonymous</author>
	<datestamp>1243784580000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>For many years, I was heavy VHDL proponent. Then I changed jobs and switched to Verilog. I now prefer the latter, but not a much I prefered VHDL in its days.</p><p>When it comes to designing an FPGA course, I would now go for Verilog, for 1 reason only: the open source Icarus Verilog simulator. It's very slow, but feature complete for what you're trying to do. There are no usable free VHDL compilers...</p></htmltext>
<tokenext>For many years , I was heavy VHDL proponent .
Then I changed jobs and switched to Verilog .
I now prefer the latter , but not a much I prefered VHDL in its days.When it comes to designing an FPGA course , I would now go for Verilog , for 1 reason only : the open source Icarus Verilog simulator .
It 's very slow , but feature complete for what you 're trying to do .
There are no usable free VHDL compilers.. .</tokentext>
<sentencetext>For many years, I was heavy VHDL proponent.
Then I changed jobs and switched to Verilog.
I now prefer the latter, but not a much I prefered VHDL in its days.When it comes to designing an FPGA course, I would now go for Verilog, for 1 reason only: the open source Icarus Verilog simulator.
It's very slow, but feature complete for what you're trying to do.
There are no usable free VHDL compilers...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160825</id>
	<title>A University Student's perspective on VHDL...</title>
	<author>file\_reaper</author>
	<datestamp>1243761540000</datestamp>
	<modclass>Informativ</modclass>
	<modscore>2</modscore>
	<htmltext><p>We were introduced to VHDL in our University's Digital Circuits course.</p><p>Most of the above commenter's have mentioned that Verilog is C like, I personally have never used or programmed in Verilog so I can't comment on that.</p><p>I did however like VHDL very much, particularly because it was *different* from C, I'm kinda growing tired of C like languages and VHDL was a breath of fresh air. It made FPGA's and the entire course in general a whole lot of fun.</p><p>It's strong typed nature was a bit cumbersome at first especially with converting std\_logic to std\_logic vectors and such because we weren't really shown how to do this or given a syntax/library reference like MSDN or Java's Documentation site.</p><p>So I'd say make a good introduction to Entities, Ports and Architectures, explain Process, Signal and Constant statements very well, also particularly highlight the strong typed nature of VHDL.</p><p>I think most of your students (such as myself) will not have done any programming in a true strongly typed language before, so this will be bit of a shock, and getting those conversions will be frustrating. (I have been there, Googling really does not help all that much)</p><p>I hope your students get as much fun out of that course as I did.</p><p>Cheers,<br>filereaper.</p></htmltext>
<tokenext>We were introduced to VHDL in our University 's Digital Circuits course.Most of the above commenter 's have mentioned that Verilog is C like , I personally have never used or programmed in Verilog so I ca n't comment on that.I did however like VHDL very much , particularly because it was * different * from C , I 'm kinda growing tired of C like languages and VHDL was a breath of fresh air .
It made FPGA 's and the entire course in general a whole lot of fun.It 's strong typed nature was a bit cumbersome at first especially with converting std \ _logic to std \ _logic vectors and such because we were n't really shown how to do this or given a syntax/library reference like MSDN or Java 's Documentation site.So I 'd say make a good introduction to Entities , Ports and Architectures , explain Process , Signal and Constant statements very well , also particularly highlight the strong typed nature of VHDL.I think most of your students ( such as myself ) will not have done any programming in a true strongly typed language before , so this will be bit of a shock , and getting those conversions will be frustrating .
( I have been there , Googling really does not help all that much ) I hope your students get as much fun out of that course as I did.Cheers,filereaper .</tokentext>
<sentencetext>We were introduced to VHDL in our University's Digital Circuits course.Most of the above commenter's have mentioned that Verilog is C like, I personally have never used or programmed in Verilog so I can't comment on that.I did however like VHDL very much, particularly because it was *different* from C, I'm kinda growing tired of C like languages and VHDL was a breath of fresh air.
It made FPGA's and the entire course in general a whole lot of fun.It's strong typed nature was a bit cumbersome at first especially with converting std\_logic to std\_logic vectors and such because we weren't really shown how to do this or given a syntax/library reference like MSDN or Java's Documentation site.So I'd say make a good introduction to Entities, Ports and Architectures, explain Process, Signal and Constant statements very well, also particularly highlight the strong typed nature of VHDL.I think most of your students (such as myself) will not have done any programming in a true strongly typed language before, so this will be bit of a shock, and getting those conversions will be frustrating.
(I have been there, Googling really does not help all that much)I hope your students get as much fun out of that course as I did.Cheers,filereaper.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28168737</id>
	<title>Tier 1 Universities teach VHDL.</title>
	<author>Zoson</author>
	<datestamp>1243874040000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Quick searches of their course listings show that they all teach Verilog as an after thought.  Many classes that mention Verilog in their course descriptions are actually listed as VHDL classes and don't mention Verilog at all in the course title.  The most apt description of the mentality is: 'this is the good way to do it, but there are others that do it this way.'</p><p>Personally, at Columbia we were taught VHDL as a virtue of our professors being from IBM and having written the actual spice software.</p></htmltext>
<tokenext>Quick searches of their course listings show that they all teach Verilog as an after thought .
Many classes that mention Verilog in their course descriptions are actually listed as VHDL classes and do n't mention Verilog at all in the course title .
The most apt description of the mentality is : 'this is the good way to do it , but there are others that do it this way .
'Personally , at Columbia we were taught VHDL as a virtue of our professors being from IBM and having written the actual spice software .</tokentext>
<sentencetext>Quick searches of their course listings show that they all teach Verilog as an after thought.
Many classes that mention Verilog in their course descriptions are actually listed as VHDL classes and don't mention Verilog at all in the course title.
The most apt description of the mentality is: 'this is the good way to do it, but there are others that do it this way.
'Personally, at Columbia we were taught VHDL as a virtue of our professors being from IBM and having written the actual spice software.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28176495</id>
	<title>Both.  And SystemC</title>
	<author>thoglette</author>
	<datestamp>1243866420000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>You must teach in VHDL.   You need to teach Verilog.</p><p>While Verilog is slowly adding features from VHDL, it's like comparing basic to e-lisp.  The semantic possibilities in VHDL are significantly larger.</p><p>However the most important thing to teach is good practice: solving the seven or eight basic fifo problems;   async vs sync reset;  various counter and adder types</p><p>Just as programmers need to grok how their code gets turned into ASM,  HDL coders need to grok the underlying hardware items that their compiler will spit out.</p><p>And verification - where you can test and were you must review.</p><p>And why coding style matters for test (eg. a parameterised loop can be verified by induction - a case statement cannot).</p><p>Particularily for chips (vs fpgas) it's got to be right first time, every time.   So you need "Code Compete" next to "Microprocessor architectures"</p><p>ps - I designed chips from the mid eighties to the early noughties.</p></htmltext>
<tokenext>You must teach in VHDL .
You need to teach Verilog.While Verilog is slowly adding features from VHDL , it 's like comparing basic to e-lisp .
The semantic possibilities in VHDL are significantly larger.However the most important thing to teach is good practice : solving the seven or eight basic fifo problems ; async vs sync reset ; various counter and adder typesJust as programmers need to grok how their code gets turned into ASM , HDL coders need to grok the underlying hardware items that their compiler will spit out.And verification - where you can test and were you must review.And why coding style matters for test ( eg .
a parameterised loop can be verified by induction - a case statement can not ) .Particularily for chips ( vs fpgas ) it 's got to be right first time , every time .
So you need " Code Compete " next to " Microprocessor architectures " ps - I designed chips from the mid eighties to the early noughties .</tokentext>
<sentencetext>You must teach in VHDL.
You need to teach Verilog.While Verilog is slowly adding features from VHDL, it's like comparing basic to e-lisp.
The semantic possibilities in VHDL are significantly larger.However the most important thing to teach is good practice: solving the seven or eight basic fifo problems;   async vs sync reset;  various counter and adder typesJust as programmers need to grok how their code gets turned into ASM,  HDL coders need to grok the underlying hardware items that their compiler will spit out.And verification - where you can test and were you must review.And why coding style matters for test (eg.
a parameterised loop can be verified by induction - a case statement cannot).Particularily for chips (vs fpgas) it's got to be right first time, every time.
So you need "Code Compete" next to "Microprocessor architectures"ps - I designed chips from the mid eighties to the early noughties.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165237</id>
	<title>LabVIEW</title>
	<author>Anonymous</author>
	<datestamp>1243847400000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>If you don't care too much about syntax or learning a new programming language then there's an FPGA-module for LabVIEW which let's you program the FPGA using graphical programming. Then there's a xilinx compiler in the background which creates the bit-file for you.</p><p>This being<nobr> <wbr></nobr>/., I'm probably going to be flamed for this...<nobr> <wbr></nobr>:)</p></htmltext>
<tokenext>If you do n't care too much about syntax or learning a new programming language then there 's an FPGA-module for LabVIEW which let 's you program the FPGA using graphical programming .
Then there 's a xilinx compiler in the background which creates the bit-file for you.This being /. , I 'm probably going to be flamed for this... : )</tokentext>
<sentencetext>If you don't care too much about syntax or learning a new programming language then there's an FPGA-module for LabVIEW which let's you program the FPGA using graphical programming.
Then there's a xilinx compiler in the background which creates the bit-file for you.This being /., I'm probably going to be flamed for this... :)</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160727</id>
	<title>Re:Where are you located?</title>
	<author>Austerity Empowers</author>
	<datestamp>1243760940000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>A lot of people compare Verilog to C, and VHDL to Pascal (ADA lite?). Either way I find that a) you will need to know both, if you are going to be in this business, b) Companies that enforce A language, in the US, enforce Verilog, companies that leave it to teams, use either VHDL or Verilog. So if you had to choose just one, and you live in the US, I say choose Verilog<nobr> <wbr></nobr>;) That said, the first ASIC I did was in VHDL (which I learned in school). I continued that in single-person FPGAs which I wrote, without objection. In my present company I was forced to learn Verilog, and I can't say that I long to go back to VHDL or have "been converted".</p><p>Both languages are designed to simulate, not synthesize. As such, the language ultimately is just the tool, "thinking hardware" in terms of the synthesizeable subsets of the languages and the realization of hardware the tools come up with is identical in both languages. The constructs that produce a given hardware are generally very parallel (in fact there's a book out there, I forget the name, that puts VHDL right next to Verilog for a given construct). Neither language is especially more compact or "R.A.D." than the other. VHDL expect to spend more time fighting your compiler and subjugating the strongly-typed aspect. Verilog expect to spend more time debugging subtle and unexpected results of improper use of the language (like C, it will do what you ask, but not always what you meant!).</p><p>I've found that Icarus is a great free Verilog simulator for Linux, and I love it, so that's a good budget choice. In general though, consider your simulation tools as the driving force in your choices. Some professional tools are better at VHDL or better at Verilog (which has a number of "versions", adding very nice features that aren't always available in a given sim). Some run far faster with one language or another. In the long run this will all balance out, but we've been saying that for a decade and there are still (increasingly small) imbalances. Examine your simulation/verification model, identify which features you may want (things like "do I want to use a large randomly accessed text file for input vectors?") and see which language offers the most robust support with your tool, and if it requires proprietary language extensions to make that happen (very common with verilog).</p><p>Most synthesizers take both and work pretty much equally with either language.</p></htmltext>
<tokenext>A lot of people compare Verilog to C , and VHDL to Pascal ( ADA lite ? ) .
Either way I find that a ) you will need to know both , if you are going to be in this business , b ) Companies that enforce A language , in the US , enforce Verilog , companies that leave it to teams , use either VHDL or Verilog .
So if you had to choose just one , and you live in the US , I say choose Verilog ; ) That said , the first ASIC I did was in VHDL ( which I learned in school ) .
I continued that in single-person FPGAs which I wrote , without objection .
In my present company I was forced to learn Verilog , and I ca n't say that I long to go back to VHDL or have " been converted " .Both languages are designed to simulate , not synthesize .
As such , the language ultimately is just the tool , " thinking hardware " in terms of the synthesizeable subsets of the languages and the realization of hardware the tools come up with is identical in both languages .
The constructs that produce a given hardware are generally very parallel ( in fact there 's a book out there , I forget the name , that puts VHDL right next to Verilog for a given construct ) .
Neither language is especially more compact or " R.A.D .
" than the other .
VHDL expect to spend more time fighting your compiler and subjugating the strongly-typed aspect .
Verilog expect to spend more time debugging subtle and unexpected results of improper use of the language ( like C , it will do what you ask , but not always what you meant !
) .I 've found that Icarus is a great free Verilog simulator for Linux , and I love it , so that 's a good budget choice .
In general though , consider your simulation tools as the driving force in your choices .
Some professional tools are better at VHDL or better at Verilog ( which has a number of " versions " , adding very nice features that are n't always available in a given sim ) .
Some run far faster with one language or another .
In the long run this will all balance out , but we 've been saying that for a decade and there are still ( increasingly small ) imbalances .
Examine your simulation/verification model , identify which features you may want ( things like " do I want to use a large randomly accessed text file for input vectors ?
" ) and see which language offers the most robust support with your tool , and if it requires proprietary language extensions to make that happen ( very common with verilog ) .Most synthesizers take both and work pretty much equally with either language .</tokentext>
<sentencetext>A lot of people compare Verilog to C, and VHDL to Pascal (ADA lite?).
Either way I find that a) you will need to know both, if you are going to be in this business, b) Companies that enforce A language, in the US, enforce Verilog, companies that leave it to teams, use either VHDL or Verilog.
So if you had to choose just one, and you live in the US, I say choose Verilog ;) That said, the first ASIC I did was in VHDL (which I learned in school).
I continued that in single-person FPGAs which I wrote, without objection.
In my present company I was forced to learn Verilog, and I can't say that I long to go back to VHDL or have "been converted".Both languages are designed to simulate, not synthesize.
As such, the language ultimately is just the tool, "thinking hardware" in terms of the synthesizeable subsets of the languages and the realization of hardware the tools come up with is identical in both languages.
The constructs that produce a given hardware are generally very parallel (in fact there's a book out there, I forget the name, that puts VHDL right next to Verilog for a given construct).
Neither language is especially more compact or "R.A.D.
" than the other.
VHDL expect to spend more time fighting your compiler and subjugating the strongly-typed aspect.
Verilog expect to spend more time debugging subtle and unexpected results of improper use of the language (like C, it will do what you ask, but not always what you meant!
).I've found that Icarus is a great free Verilog simulator for Linux, and I love it, so that's a good budget choice.
In general though, consider your simulation tools as the driving force in your choices.
Some professional tools are better at VHDL or better at Verilog (which has a number of "versions", adding very nice features that aren't always available in a given sim).
Some run far faster with one language or another.
In the long run this will all balance out, but we've been saying that for a decade and there are still (increasingly small) imbalances.
Examine your simulation/verification model, identify which features you may want (things like "do I want to use a large randomly accessed text file for input vectors?
") and see which language offers the most robust support with your tool, and if it requires proprietary language extensions to make that happen (very common with verilog).Most synthesizers take both and work pretty much equally with either language.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161575</id>
	<title>Try Handel C</title>
	<author>Anonymous</author>
	<datestamp>1243768020000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Handel C is the best language if you can find it...</p></htmltext>
<tokenext>Handel C is the best language if you can find it.. .</tokentext>
<sentencetext>Handel C is the best language if you can find it...</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160509</id>
	<title>Once Verilog supported signed arithmetic...</title>
	<author>chrispitude</author>
	<datestamp>1243802700000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>...it was game over.  I was a staunch believer in VHDL and its many features (generics, records, operator overloading, strong type checking).  But once Verilog implemented proper signed arithmetic which didn't require tedious manual sign extension in the code, then I never looked back.  SystemVerilog continues to push Verilog forward.  gwait (179005) had the right idea - start with Verilog, and if you ever need to work with VHDL, you will have a much better idea of what aspects of the VHDL language you do and don't need to learn.</htmltext>
<tokenext>...it was game over .
I was a staunch believer in VHDL and its many features ( generics , records , operator overloading , strong type checking ) .
But once Verilog implemented proper signed arithmetic which did n't require tedious manual sign extension in the code , then I never looked back .
SystemVerilog continues to push Verilog forward .
gwait ( 179005 ) had the right idea - start with Verilog , and if you ever need to work with VHDL , you will have a much better idea of what aspects of the VHDL language you do and do n't need to learn .</tokentext>
<sentencetext>...it was game over.
I was a staunch believer in VHDL and its many features (generics, records, operator overloading, strong type checking).
But once Verilog implemented proper signed arithmetic which didn't require tedious manual sign extension in the code, then I never looked back.
SystemVerilog continues to push Verilog forward.
gwait (179005) had the right idea - start with Verilog, and if you ever need to work with VHDL, you will have a much better idea of what aspects of the VHDL language you do and don't need to learn.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160045</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243799040000</datestamp>
	<modclass>Redundant</modclass>
	<modscore>-1</modscore>
	<htmltext><p>Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.</p><p>In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.</p><p>Personally, I prefer VHDL.</p></htmltext>
<tokenext>Personally , I would say that Verilog is more C-like : weakly typed , compact , efficient notation , whereas VHDL is much more Ada-like : strongly typed , often verbose , but can catch errors that the other one ca n't.In industry , as far as I can tell , Verilog seems to be more used in North America and VHDL in Europe , so that might affect what you care about , too.Personally , I prefer VHDL .</tokentext>
<sentencetext>Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.Personally, I prefer VHDL.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160605</id>
	<title>Either or Neither</title>
	<author>kj\_cmpe</author>
	<datestamp>1243803360000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext>As other people have pointed out, the important thing is that neither Verilog or VHDL are sequential programming languages... They are hardware description languages, or could be thought of as parallel programming languages or simulation languages. In any case, students will make the biggest mistakes by: 1. Thinking that it's just like C/C++/Java/whatever, and 2.Using features of either language (which are both quite powerful), but that are unsynthesizeable.
<br> <br>
Thus, an important part of any course on HDL should have a heavy focus on synthesizeable code, with many iterations of seeing not just the "right" way to do things, but why that is the right way and the alternatives wouldn't produce the same (presumably good) hardware as the alternative ways that look or seem similar.
<br> <br>
There are many other languages to consider as well that may or may not end up being used widely in industry.. a sampling is...<br>
SystemC<br>
HandelC<br>
BluSpec<br> <br>

Plus, there are many C-to-Verilog, C-to-VHDL or C-to-HW compilers out there that try to jump from sequential code with pragmas etc. to the HW.... <br> <br>

In general, I would suggest thinking of this not as a language course, but as a hardware design course where the tools used happen to include a new language (for the students). It would be easy to concentrate on language syntax and end up with students that know syntax, but not how to make good HW descriptions....</htmltext>
<tokenext>As other people have pointed out , the important thing is that neither Verilog or VHDL are sequential programming languages... They are hardware description languages , or could be thought of as parallel programming languages or simulation languages .
In any case , students will make the biggest mistakes by : 1 .
Thinking that it 's just like C/C + + /Java/whatever , and 2.Using features of either language ( which are both quite powerful ) , but that are unsynthesizeable .
Thus , an important part of any course on HDL should have a heavy focus on synthesizeable code , with many iterations of seeing not just the " right " way to do things , but why that is the right way and the alternatives would n't produce the same ( presumably good ) hardware as the alternative ways that look or seem similar .
There are many other languages to consider as well that may or may not end up being used widely in industry.. a sampling is.. . SystemC HandelC BluSpec Plus , there are many C-to-Verilog , C-to-VHDL or C-to-HW compilers out there that try to jump from sequential code with pragmas etc .
to the HW... . In general , I would suggest thinking of this not as a language course , but as a hardware design course where the tools used happen to include a new language ( for the students ) .
It would be easy to concentrate on language syntax and end up with students that know syntax , but not how to make good HW descriptions... .</tokentext>
<sentencetext>As other people have pointed out, the important thing is that neither Verilog or VHDL are sequential programming languages... They are hardware description languages, or could be thought of as parallel programming languages or simulation languages.
In any case, students will make the biggest mistakes by: 1.
Thinking that it's just like C/C++/Java/whatever, and 2.Using features of either language (which are both quite powerful), but that are unsynthesizeable.
Thus, an important part of any course on HDL should have a heavy focus on synthesizeable code, with many iterations of seeing not just the "right" way to do things, but why that is the right way and the alternatives wouldn't produce the same (presumably good) hardware as the alternative ways that look or seem similar.
There are many other languages to consider as well that may or may not end up being used widely in industry.. a sampling is...
SystemC
HandelC
BluSpec 

Plus, there are many C-to-Verilog, C-to-VHDL or C-to-HW compilers out there that try to jump from sequential code with pragmas etc.
to the HW....  

In general, I would suggest thinking of this not as a language course, but as a hardware design course where the tools used happen to include a new language (for the students).
It would be easy to concentrate on language syntax and end up with students that know syntax, but not how to make good HW descriptions....</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28165181</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243889820000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>VHDL as it forces the programer to be more specific about their intent.  I have had a few cases where I have ended up synthersising something very different to what I actualy wanted in verilog.</p></htmltext>
<tokenext>VHDL as it forces the programer to be more specific about their intent .
I have had a few cases where I have ended up synthersising something very different to what I actualy wanted in verilog .</tokentext>
<sentencetext>VHDL as it forces the programer to be more specific about their intent.
I have had a few cases where I have ended up synthersising something very different to what I actualy wanted in verilog.</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159981</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159945</id>
	<title>Re:Where are you located?</title>
	<author>Anonymous</author>
	<datestamp>1243798500000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>Military uses (and created) VHDL in America.</p><p>Or, rather, the DoD created VHDL way back when, so all stuff done with the military/defense department/gubment is done in VHDL.</p><p>But yes, the US private sector generally uses Verilog.  (Other N. American countries, I can't say)</p></htmltext>
<tokenext>Military uses ( and created ) VHDL in America.Or , rather , the DoD created VHDL way back when , so all stuff done with the military/defense department/gubment is done in VHDL.But yes , the US private sector generally uses Verilog .
( Other N. American countries , I ca n't say )</tokentext>
<sentencetext>Military uses (and created) VHDL in America.Or, rather, the DoD created VHDL way back when, so all stuff done with the military/defense department/gubment is done in VHDL.But yes, the US private sector generally uses Verilog.
(Other N. American countries, I can't say)</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28159869</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28160703</id>
	<title>learn digital design, then learn syntax</title>
	<author>rsw</author>
	<datestamp>1243760760000</datestamp>
	<modclass>Insightful</modclass>
	<modscore>2</modscore>
	<htmltext>I work at a mixed signal IC company that is, on the digital side, principally a Verilog shop.  We do have one or two projects that use VHDL, and maybe even one or two that use both.  From a practical applicability point of view, Verilog is a bit more popular as far as I know, but this should not be taken to imply that you will do your students a disservice teaching them VHDL.  When we interview digital designers, we don't ask them "do you know Verilog?" we ask them "do you know digital design?"  The language is far far less important than the underlying concepts.
<br> <br>
The biggest mistake you can make is concentrating on the language and expecting the programming skills will apply to digital design just because the syntax of Verilog looks like the syntax of C (or VHDL looks like Pascal, if you squint a lot).  First, learn how to do digital design, then learn how to describe those designs in an HDL.  Things might go slightly faster if you are familiar with the syntactic structures (i.e., C coders will feel more comfortable using Verilog), but trying to take the "do-while--if-then-else--for" mentality of a procedural coder and trying to jam it into an FPGA is going to be a painful road to failure.
<br> <br>
It's time for a bad analogy!  "Hey guys, I have a bunch of novelists whom I want to teach to write medical textbooks.  Should I teach them to do it in English, or Spanish?"  The answer is "whichever they're more familiar with already... but first teach them medicine."
<br> <br>
-=rsw</htmltext>
<tokenext>I work at a mixed signal IC company that is , on the digital side , principally a Verilog shop .
We do have one or two projects that use VHDL , and maybe even one or two that use both .
From a practical applicability point of view , Verilog is a bit more popular as far as I know , but this should not be taken to imply that you will do your students a disservice teaching them VHDL .
When we interview digital designers , we do n't ask them " do you know Verilog ?
" we ask them " do you know digital design ?
" The language is far far less important than the underlying concepts .
The biggest mistake you can make is concentrating on the language and expecting the programming skills will apply to digital design just because the syntax of Verilog looks like the syntax of C ( or VHDL looks like Pascal , if you squint a lot ) .
First , learn how to do digital design , then learn how to describe those designs in an HDL .
Things might go slightly faster if you are familiar with the syntactic structures ( i.e. , C coders will feel more comfortable using Verilog ) , but trying to take the " do-while--if-then-else--for " mentality of a procedural coder and trying to jam it into an FPGA is going to be a painful road to failure .
It 's time for a bad analogy !
" Hey guys , I have a bunch of novelists whom I want to teach to write medical textbooks .
Should I teach them to do it in English , or Spanish ?
" The answer is " whichever they 're more familiar with already... but first teach them medicine .
" - = rsw</tokentext>
<sentencetext>I work at a mixed signal IC company that is, on the digital side, principally a Verilog shop.
We do have one or two projects that use VHDL, and maybe even one or two that use both.
From a practical applicability point of view, Verilog is a bit more popular as far as I know, but this should not be taken to imply that you will do your students a disservice teaching them VHDL.
When we interview digital designers, we don't ask them "do you know Verilog?
" we ask them "do you know digital design?
"  The language is far far less important than the underlying concepts.
The biggest mistake you can make is concentrating on the language and expecting the programming skills will apply to digital design just because the syntax of Verilog looks like the syntax of C (or VHDL looks like Pascal, if you squint a lot).
First, learn how to do digital design, then learn how to describe those designs in an HDL.
Things might go slightly faster if you are familiar with the syntactic structures (i.e., C coders will feel more comfortable using Verilog), but trying to take the "do-while--if-then-else--for" mentality of a procedural coder and trying to jam it into an FPGA is going to be a painful road to failure.
It's time for a bad analogy!
"Hey guys, I have a bunch of novelists whom I want to teach to write medical textbooks.
Should I teach them to do it in English, or Spanish?
"  The answer is "whichever they're more familiar with already... but first teach them medicine.
"
 
-=rsw</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161321</id>
	<title>Depends on the product and industry.</title>
	<author>asm2750</author>
	<datestamp>1243765980000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>VHDL is used by defense contractors still. Although its ADA based, it requires strong typing, making it less prone to error. Although its hard to learn at first, you eventually notice its a lot like working with a virtual breadboard of sorts. Verilog is used in mostly consumer devices, and ASIC design. Intel, AMD, and other chip companies use verilog to design their newer architectures, although it can be more prone to bugs than VHDL, neither language is absolutely perfect. This is why we have verification and test engineers write test benches for the code to find any errors in the design.<br> <br>In this day and age, its best to know both languages. They are pretty much alike, just that some of the keywords and syntax is different. Most FPGA design tools come with soft processors made in VHDL or verilog, and the user will typically use C to create the for the processor to run your task, this alone also makes knowing C a requirement. VHDL and verilog in such projects would be then used to special tasks, like fast image or audio processing, since the VHDL or verilog module would be tuned for that task and be able to complete it in a very short order of time compared to a general purpose processor. If I can make any recommendations, the sites <a href="http://www.asic-world.com/" title="asic-world.com" rel="nofollow">http://www.asic-world.com/</a> [asic-world.com] and <a href="http://www.fpga4fun.com/" title="fpga4fun.com" rel="nofollow">http://www.fpga4fun.com/</a> [fpga4fun.com] are two places I would look to first when start learning about verilog and VHDL.</htmltext>
<tokenext>VHDL is used by defense contractors still .
Although its ADA based , it requires strong typing , making it less prone to error .
Although its hard to learn at first , you eventually notice its a lot like working with a virtual breadboard of sorts .
Verilog is used in mostly consumer devices , and ASIC design .
Intel , AMD , and other chip companies use verilog to design their newer architectures , although it can be more prone to bugs than VHDL , neither language is absolutely perfect .
This is why we have verification and test engineers write test benches for the code to find any errors in the design .
In this day and age , its best to know both languages .
They are pretty much alike , just that some of the keywords and syntax is different .
Most FPGA design tools come with soft processors made in VHDL or verilog , and the user will typically use C to create the for the processor to run your task , this alone also makes knowing C a requirement .
VHDL and verilog in such projects would be then used to special tasks , like fast image or audio processing , since the VHDL or verilog module would be tuned for that task and be able to complete it in a very short order of time compared to a general purpose processor .
If I can make any recommendations , the sites http : //www.asic-world.com/ [ asic-world.com ] and http : //www.fpga4fun.com/ [ fpga4fun.com ] are two places I would look to first when start learning about verilog and VHDL .</tokentext>
<sentencetext>VHDL is used by defense contractors still.
Although its ADA based, it requires strong typing, making it less prone to error.
Although its hard to learn at first, you eventually notice its a lot like working with a virtual breadboard of sorts.
Verilog is used in mostly consumer devices, and ASIC design.
Intel, AMD, and other chip companies use verilog to design their newer architectures, although it can be more prone to bugs than VHDL, neither language is absolutely perfect.
This is why we have verification and test engineers write test benches for the code to find any errors in the design.
In this day and age, its best to know both languages.
They are pretty much alike, just that some of the keywords and syntax is different.
Most FPGA design tools come with soft processors made in VHDL or verilog, and the user will typically use C to create the for the processor to run your task, this alone also makes knowing C a requirement.
VHDL and verilog in such projects would be then used to special tasks, like fast image or audio processing, since the VHDL or verilog module would be tuned for that task and be able to complete it in a very short order of time compared to a general purpose processor.
If I can make any recommendations, the sites http://www.asic-world.com/ [asic-world.com] and http://www.fpga4fun.com/ [fpga4fun.com] are two places I would look to first when start learning about verilog and VHDL.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28162931</id>
	<title>Probably Verilog</title>
	<author>uarch</author>
	<datestamp>1243779960000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext><p>Much of the industry appears to be shifting towards Verilog but VHDL is still very common and is not going to disappear any time soon.  If I had to make that decision I'd most likely choose Verilog because of this but it's not a simple, clear-cut choice.</p><p>When I used to teach Verilog to college seniors &amp; grad students I saw the syntax similarity to C as a problem for many students.  Every one of them had a strong programming background and were used to the sequential nature of software.  When you let them loose with some of the Verilog constructs it will take a while for most of them to understand the parallel nature of what the language is describing - I can't begin to count the number of times I saw someone try to 'call' a piece of hardware as a process or part of a for-loop as if it magically appeared to calculate a single result and then vanished into never-never land.  Blocking &amp; non-blocking assignments will also cause countless headaches.  So will the ease at which you can throw down massive amounts of hardware with a few simple lines of Verilog.  You can and will see students make similar mistakes with VHDL but I believe the syntax differences can help limit the problems.</p><p>Ultimately, if the students need to use one in their career they will also need to use the other.  No matter which one you choose they will easily be able to pick up the other as long as they understand what the HDL is truly describing.</p></htmltext>
<tokenext>Much of the industry appears to be shifting towards Verilog but VHDL is still very common and is not going to disappear any time soon .
If I had to make that decision I 'd most likely choose Verilog because of this but it 's not a simple , clear-cut choice.When I used to teach Verilog to college seniors &amp; grad students I saw the syntax similarity to C as a problem for many students .
Every one of them had a strong programming background and were used to the sequential nature of software .
When you let them loose with some of the Verilog constructs it will take a while for most of them to understand the parallel nature of what the language is describing - I ca n't begin to count the number of times I saw someone try to 'call ' a piece of hardware as a process or part of a for-loop as if it magically appeared to calculate a single result and then vanished into never-never land .
Blocking &amp; non-blocking assignments will also cause countless headaches .
So will the ease at which you can throw down massive amounts of hardware with a few simple lines of Verilog .
You can and will see students make similar mistakes with VHDL but I believe the syntax differences can help limit the problems.Ultimately , if the students need to use one in their career they will also need to use the other .
No matter which one you choose they will easily be able to pick up the other as long as they understand what the HDL is truly describing .</tokentext>
<sentencetext>Much of the industry appears to be shifting towards Verilog but VHDL is still very common and is not going to disappear any time soon.
If I had to make that decision I'd most likely choose Verilog because of this but it's not a simple, clear-cut choice.When I used to teach Verilog to college seniors &amp; grad students I saw the syntax similarity to C as a problem for many students.
Every one of them had a strong programming background and were used to the sequential nature of software.
When you let them loose with some of the Verilog constructs it will take a while for most of them to understand the parallel nature of what the language is describing - I can't begin to count the number of times I saw someone try to 'call' a piece of hardware as a process or part of a for-loop as if it magically appeared to calculate a single result and then vanished into never-never land.
Blocking &amp; non-blocking assignments will also cause countless headaches.
So will the ease at which you can throw down massive amounts of hardware with a few simple lines of Verilog.
You can and will see students make similar mistakes with VHDL but I believe the syntax differences can help limit the problems.Ultimately, if the students need to use one in their career they will also need to use the other.
No matter which one you choose they will easily be able to pick up the other as long as they understand what the HDL is truly describing.</sentencetext>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161397</id>
	<title>Re:FPGA SDK's for Student's to work on...</title>
	<author>brendank310</author>
	<datestamp>1243766520000</datestamp>
	<modclass>None</modclass>
	<modscore>1</modscore>
	<htmltext>Digilent Basys Board</htmltext>
<tokenext>Digilent Basys Board</tokentext>
<sentencetext>Digilent Basys Board</sentencetext>
	<parent>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28161007</parent>
</comment>
<comment>
	<id>http://www.semanticweb.org/ontologies/ConversationInstances.owl#comment09_05_31_187208.28163871</id>
	<title>We did study this...</title>
	<author>Anonymous</author>
	<datestamp>1243787520000</datestamp>
	<modclass>None</modclass>
	<modscore>0</modscore>
	<htmltext><p>In my second and third years of undergrad, we studied VHDL (one class each year).  If I remember correctly VHDL is more based in the DoD attempts at standardization from the days when FPGAs were very first being developed.  The professor told us that once we've got VHDL down, Verilog is supposedly very similar.  Since that time, I've studied FPGAs independently on and off since they're really interesting.  It seems that any tool capable of building systems off one can also build off the other.  Honestly, I haven't even really seen any Verilog code...ever.</p></htmltext>
<tokenext>In my second and third years of undergrad , we studied VHDL ( one class each year ) .
If I remember correctly VHDL is more based in the DoD attempts at standardization from the days when FPGAs were very first being developed .
The professor told us that once we 've got VHDL down , Verilog is supposedly very similar .
Since that time , I 've studied FPGAs independently on and off since they 're really interesting .
It seems that any tool capable of building systems off one can also build off the other .
Honestly , I have n't even really seen any Verilog code...ever .</tokentext>
<sentencetext>In my second and third years of undergrad, we studied VHDL (one class each year).
If I remember correctly VHDL is more based in the DoD attempts at standardization from the days when FPGAs were very first being developed.
The professor told us that once we've got VHDL down, Verilog is supposedly very similar.
Since that time, I've studied FPGAs independently on and off since they're really interesting.
It seems that any tool capable of building systems off one can also build off the other.
Honestly, I haven't even really seen any Verilog code...ever.</sentencetext>
</comment>
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