RISC-V Assembly Resources

CS 3410 uses the 64-bit RISC-V (pronounced risk-five) instruction set architecture (ISA). RISC-V is a modern reduced instruction set computer (RISC) architecture. RISC-V is unique because it’s an open instruction set that anyone can implement without any kind of licensing. (That’s in contrast to the two most popular ISAs, Arm and x86, which both require expensive licenses to implement in hardware.)

Here are some references you might find helpful when writing and reading RISC-V assembly code.

Reference Materials

• This short reference sheet contains instruction encodings for RISC-V 32, RISC-V 64, and beyond.
• For the definitive description of what every instruction does and how it’s encoded, see the official ISA manual. It’s long, though, and can get a little bit technical.
• Try this simple RISC-V reference page for another look at all the instructions.

Online Tools

Cornell’s new experimental RISC-V interpreter lets you run RISC-V programs in your browser. You can step through instructions one at a time and observe their effects on registers and memory. (This replaces an old in-browser interpreter, which we’re not linking to here, that only supports the 32-bit version of the RISC-V ISA. CS 3410 uses the 64-bit version.)