Input your RISC-V code here:


The most recent instructions will be shown here when stepping.

Features

  • Reset to load the code, Step one instruction, or Run all instructions
  • Set a breakpoint by clicking on the line number (only for Run)
  • View registers on the right, memory on the bottom of this page

Supported Instructions

  • Arithmetics: ADD, ADDI, SUB
  • Logical: AND,ANDI,OR,ORI, XOR,XORI
  • Sets: SLT, SLTI, SLTU, SLTIU
  • Shifts: SRA, SRAI, SRL, SRLISLL, SLLI
  • Memory: LW, SW, LB, SB
  • PC: LUI, AUIPC
  • Jumps: JAL, JALR
  • Branches: BEQ, BNE,BLT, BGE, BLTU, BGEU

RISC-V Reference: riscv-spec-v2.2.pdf

Init Value Register Decimal Hex Binary
0x0 (zero)00x000000000b00000000000000000000000000000000
x1 (ra)00x000000000b00000000000000000000000000000000
x2 (sp)00x000000000b00000000000000000000000000000000
x3 (gp)00x000000000b00000000000000000000000000000000
x4 (tp)00x000000000b00000000000000000000000000000000
x5 (t0)00x000000000b00000000000000000000000000000000
x6 (t1)00x000000000b00000000000000000000000000000000
x7 (t2)00x000000000b00000000000000000000000000000000
x8 (s0/fp)00x000000000b00000000000000000000000000000000
x9 (s1)00x000000000b00000000000000000000000000000000
x10 (a0)00x000000000b00000000000000000000000000000000
x11 (a1)00x000000000b00000000000000000000000000000000
x12 (a2)00x000000000b00000000000000000000000000000000
x13 (a3)00x000000000b00000000000000000000000000000000
x14 (a4)00x000000000b00000000000000000000000000000000
x15 (a5)00x000000000b00000000000000000000000000000000
x16 (a6)00x000000000b00000000000000000000000000000000
x17 (a7)00x000000000b00000000000000000000000000000000
x18 (s2)00x000000000b00000000000000000000000000000000
x19 (s3)00x000000000b00000000000000000000000000000000
x20 (s4)00x000000000b00000000000000000000000000000000
x21 (s5)00x000000000b00000000000000000000000000000000
x22 (s6)00x000000000b00000000000000000000000000000000
x23 (s7)00x000000000b00000000000000000000000000000000
x24 (s8)00x000000000b00000000000000000000000000000000
x25 (s9)00x000000000b00000000000000000000000000000000
x26 (s10)00x000000000b00000000000000000000000000000000
x27 (s11)00x000000000b00000000000000000000000000000000
x28 (t3)00x000000000b00000000000000000000000000000000
x29 (t4)00x000000000b00000000000000000000000000000000
x30 (t5)00x000000000b00000000000000000000000000000000
x31 (t6)00x000000000b00000000000000000000000000000000


Memory Address Decimal Hex Binary
0x0000000000x000000000b00000000000000000000000000000000
0x0000000400x000000000b00000000000000000000000000000000
0x0000000800x000000000b00000000000000000000000000000000
0x0000000c00x000000000b00000000000000000000000000000000
0x0000001000x000000000b00000000000000000000000000000000
0x0000001400x000000000b00000000000000000000000000000000
0x0000001800x000000000b00000000000000000000000000000000
0x0000001c00x000000000b00000000000000000000000000000000
0x0000002000x000000000b00000000000000000000000000000000
0x0000002400x000000000b00000000000000000000000000000000
Credit to Danny Qiu for the creation of the original MIPS interpreter.