You must work ALONE for this and all other homeworks. You will work in groups only for projects. Updates to this assignment will be posted on the course web page.
8b/10b encoding was proposed by Albert X. Widmer and Peter A. Franaszek of IBM Corporation in 1983. The code defines the mapping from a 8-bit byte (256 unique data words) and an additional 12 special (or K) characters into a 10-bit symbol, hence the name 8b/10b encoding. It has been widely used in high speed serial communication standards that need a run-length limited, DC balanced data stream for reliable data transmission and clock recovery. Because of its many feature, the code has been used in the physical layer (PHY) of a number of current and emerging standards, including Fibre Channel, Gigabit Ethernet, and Rapid I/O, to name a few.
The code scheme is DC-balanced, which is of particular advantage on AC-coupled electrical connections to avoid voltage imbalance problem between connected systems or components. In the other word, DC-balance means that the generated bit-stream from the encoder has equal number of zeros and ones in the long term. For this assignment, you need to make sure that the encoder you have designed maintains the DC-balance property of the generated bit-stream.
Academic Integrity. You may consult any documentation available to you. But we expect your design to be entirely your own, and your submission should cite any significant sources of information you used. If you are unsure if it is okay to borrow from some other source, just ask the TAs. If you are hesitant to ask the TAs or to cite the source, then it is probably not okay. Plagiarism in any form will not be tolerated. It is also your responsibility to make sure your sources match the material we describe here.
In this section, we explain the functionality of the encoder in more details. Your design should implement all the features mentioned in this section. We have borrowed a few terms from the original IBM patent. Understanding them clearly is crucial to a successful implementation of the encoder. The most important terminology to understand for this assignment is disparity.
The disparity of any block of data is defined as the difference between the number of ones and zeros in the block. Positive and negative refer to an excess of 1s over 0s, or 0s over 1s, respectively. Each encoded symbol can be considered to be a block. The code scheme guarantees that an encoded symbol's disparity is always either 0 (five ones, five zeros), +2 (six ones four zeros) or -2 (four ones, six zeros). Some byte inputs will have more that one potential symbol encoding with the encoded symbol pattern determined by the "running disparity". Running disparity is simply a record of disparity for the aggregate of all the previously encoded symbols. For packet-based networking applications, the running disparity is typically tracked from the start of a packet. The code scheme stipulates that the running disparity at the end of any symbol (block) is always +1 or -1. To ensure that this rule is maintained, the Encoder will track the current running disparity. If the currently encoded byte produces a symbol of zero disparity, the running disparity remains unchanged. When the input byte produces a nonzero disparity symbol, the Encoder will encode the data such that the running disparity is swapped, for example, [+1 + (-2) = -1] or [-1 +(+2) = +1]. See Table 1 for an example of the two possible encoded symbol patterns for the D31.1 data symbol.
The code scheme actually partitions the input byte into 5-bit and 3-bit sub-blocks, which in turn are encoded into 6- and 4-bit blocks respectively. The original nomenclature defines the symbols in terms of these sub-blocks. The five input bits are defined as A, B, C, D and E (A is LSB) and the 3-bit block is F, G and H (F is LSB). A prefix of D or K is used to distinguish between data and special characters respectively. For example, D31.1 is a data symbol with all ones on the 5-bit block (11111) and a single one as the LSB of the 3-bit block (100) (see Table 1). Note that the 5-bit sub-block precedes the 3-bit sub-block and the ordering (LSB to MSB) is ABCDE_FGH. The encoded sub-blocks are described with lowercase letters a, b, c, d, e, i (i is LSB) and f, g, h, j (j is LSB) respectively, and the ordering is (LSB to MSB) jhgf_iedcba. See Appendix A for the mapping between input bytes and output bits.
The encoder assumes a negative RD- (-1) at start up. When a 8-bit data is encoding, the encoder will use the RD- column for encoding. If the 10-bit data been encoded is disparity neutral, the Running Disparity will not be changed and the RD- column will still be used. Otherwise, the Running Disparity will be changed and the RD+ column will be used instead. Similarly, if the current Running Disparity is positive (RD+) and a disparity neutral 10-bit data is encoded, the Running Disparity will still be RD+. Otherwise, it will be changed from RD+ to RD- and the RD- column will be used again.
| Din[7:0] | DOut [9:0] | |||||||||||||||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | RD (prior) | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | RD (after) | |
| H | G | F | E | D | C | B | A | j | h | g | f | i | e | d | c | b | a | |||
| D31.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | +1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | -1 |
| D31.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | -1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | +1 |
Table 1: Example Encoding of D31.1 for both running disparity (RD) cases
In this assignment, you will need to build an encoder that receives 8-bit symbols from data_in[7:0], and outputs encoded 10-bit symbols at data_out[9:0]. The encoder is driven by a clock signal. The master reset reset_n will reset all internal registers of the encoder to their initial states.
Optional task The encoder also takes an k_in input. The k_in input controls whether the data_in should be encoded as data (k_in = 0) or special character (k_in=1). If k_in was active and data_in did not map to any special character, an k_err output becomes active (High).
You may build any circuit that implements the behavior described above. One possible design is to split the design into three parts: first, build a datapath to do the encoding; second, building a finite state machine to maintain the running disparity and control the encoding datapath; third, building the interface between the encoder and external environment. You are not required to follow the design suggested here.
Part 1: Datapath
| Inputs: | data_in[8], sel |
| Outputs: | data_out[10] |
One way to implement the mapping between input symbols and output symbols is by using a hardware lookup table (LUT). In digital logic, an n-bit lookup table can be implemented with a multiplexer whose select lines are the inputs of the LUT and whose outputs are constants. Alternatively, you could use the ROM component in Logisim to implement a hardware lookup table. The input port to the ROM specifies the address of the word that is accessed. The output port returns the content at the particular address which is specified by the input. The ROM in Logisim is customizable, you may change the input and output bitwidth to fit your need. We assume in this assignment that, the access time for the ROM is one clock cycle, i.e., the content in the ROM at the address that you specified is available within the same clock cycle.
Part 2: Finite State Machine
| Inputs: | data_in[10], Clock, Reset_n |
| Outputs: | sel |
The running disparity is maintained by storing the current disparity in a register. Each time an new output symbol is generated, the current disparity should be updated by adding the value stored in the register with the parity of the output symbol. Note that this operation is completely internal to the encoder, and should be not visible to the external world. You are free to choose how many states you need for the FSM and what state encoding is used. Minimizing the number of bits used to encode states helps with simplifying your circuit.
Part 3: Putting it all together
| Inputs: | data_in[8], Clock, Reset_n |
| Outputs: | data_out[10] |
For this assignment, we assume that the encoder receives a 8-bit symbol every clock cycle. Similarly, a new 10-bit symbol should be generated at every clock cycle. Note that the 8-bit symbol could be either Dx.y, or Kx.y.
Complexity: The encoder design is not large. If you use more than a handful of components for the datapath or interface, for example, you are probably working too hard. The finite state machine can be done with only a few states, and most of the outputs of the finite state machine part are trivial.
Hardware Lookup Table: The hardware lookup table can be of great help to simplify your logic. Consider using them in the design for encoding table and running disparity calculation.
Clock: For debugging, you can put a Logisim "Clock" into your circuit and set Logisim to toggle the clock one step at a time, or automatically at a set frequency. It is best to use a single clock for your entire circuit.
Getting help: Ask the course staff for help. If you suspect a bug in Logisim, contact cs3410-staff-l@cs.cornell.edu. There is a known bug having to do with bus splitters when the simulation is running. It is best to turn the simulator off when editing the wire ordering on a bus splitter. This does not cause any data loss, but you might have to restart Logisim.
Submit single Logisim project file containing all of your circuits. The top-level circuit should be called "Encoder", and should have the same input and outputs as given in the skeleton circuit provided. Testing is up to you, and you do not need to submit any documentation beyond your well-labeled Logisim circuits.
For partial credit you may submit, if you desire, a document (text, PDF, or word) containing an explanation of your circuit or your design in addition to or instead of a Logisim circuit. You should do this if you are unsure that your circuit is correct, or if you think your circuit is so complex as to not be self-explanatory, or you aren't able to get something working in Logisim.
The internet has lots of information about the 8b/10b encoding. Use them wisely and judgmentally. There is no guarantee on the correctness of the information on the internet. Ask your TA if you hesitate.
The Appendix has the entire 8b/10b encode table listed in it. Be smart about using it!
Encoding table sorted by Dxx.pdf
Encoding table sorted by Dy.pdf
For the adventurous, Implement the encoding of K(control) characters in your encoder. Submit a separate Logisim project file containing all of your circuits for bonus point design. The top_level circuit should be called "encoder_bonus", and should have additional input k_in and additional output k_err.