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The 314/cpuparts.cast file contains a number of useful
definitions. These definitions were used to construct the register file
provided in 314/rf.cast.
| Definition |
Description |
TInv() (node in,en,_out); |
Tri-state inverter (see lecture notes). |
TInvE() (node in,en,_en,_out); |
Tri-state inverter, but the inverted en signal is exposed. This is
used when balancing the load of both en and _en for
performance reasons. |
SignalRamp(int N) (node in,out);
_SignalRamp(int N) (node in,_out);
SignalDRamp(int N) (node in,out,_out);
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These definitions use a number of inverters to speed up a signal (as described
in class). out gets the same value as in, but can be
connected to N gates without much slowdown, and _out is
the inverted version of in, but can be connected to N
gates without much slowdown. (This turns what is normally a linear delay into a
logarithmic one.)
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TMux2to1(int N) (node[N] a,b; node sel; node[N] out); |
N-bit 2-to-1 mux built using the tristate inverters and signal
ramp definitions. If sel is 0, it selects a otherwise
selects b.
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TBusMux2to1(int N) (Bus(N) a,b; node sel; Bus(N) out); |
Uses Bus inputs and outputs instead of an array of nodes.
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Decode32() (node[5] in; node[32] out); |
A 5-to-32 decoder designed using the signal ramp definitions. This definition
is instructive, and is discussed below.
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posBusFLOP(int N) (Bus(N) in,out); |
out is the flop'ed version of in. Convenient
shorthand when defining major pipeline registers.
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The 5-to-32 decoder definition shows how one can compactly describe reasonably
complex circuits by observing patterns in the gate description. The definition
given is: define Decode32() (node[5] in; node[32] out)
{
node[2,5] IN;
<i:5: SignalDRamp(32) (in[i],IN[1,i],IN[0,i]);>
<i:32: "314/And5"() (IN[i%2,0], IN[(i/2)%2,1], IN[(i/4)%2,2],
IN[(i/8)%2,3], IN[(i/16)%2,4], out[i]);>
}
If the input in is 00110, we want out[6] to
be 1 and all the other output signals to be 0. The logic equation for out[6]
can be determined from the binary representation for the number 6. The equation
is !in[4]&!in[3]&in[2]&in[1]&!in[0] (use a NOT
when the input should be a zero). Each output signal can therefore be generated
using a 5-input AND gate, and the inputs to the AND gate for output out[i]
can be determined from the binary representation of i, using div
and mod.
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