Section notes for CS162 Section #9, April 1, 2003 Hakim Weatherspoon - Administrivia - Office hours this week Tues 3:30- 4:30 5th floor Soda alcove Wed 11:30-12:30 location TBD - Project 2 Code Thur 4/3 - Project 3 Initial Design Doc Tue 4/15 - Project 3 Design Reviews Wed 4/16 - Project 3 Code Due Thur 4/24 QUIZ DEMAND PAGING What happens on a page fault (everything from A to Z)?!!! Pg. 326 and 323 of dinosaur book. 1. Trap to the operating system. 2. Save the user registers and process state 3. Determinte the interrupt was a page fault 4. Check that the page reference was legal and determine the location of the page on disk. 5. Issue a read from the disk toa a free frame: a. Wait in a queue for this device until the read request is serviced. b. Wait for the device seek and/or latency time. c. Begin the transfer of the page to a free frame. 6. While waiting, allocate the CPU to some other user (CPU scheduling optional). 7. Interrupt from the disk (I/O completed). 8. Save the registers and process state for the other uster (if step 6 is executed). 9. Determine that the interrupt was from the disk. 10. Correct the page table and other tables to show that the desired page is now in memory. 11. Wait for the CPU to be allocated to this process again. 12. Resotre the user registers, process state, and new page table, then resume the interrupted instruction. -or- 1. We check an internal table (usually kept with the process control block) for this process, to determine whether the references was a valid or invalid memory access. 2. If the reference was invalid, we terminate the process. If it was valid, but have not yet brought in that page, we now page it in. 3. We find a free frame (by taking one from the free-fram list, for example). 4. We schedule a disk operation to read the desired page into the newly allocated frame. 5. When the disk read is complete, we modify the internal table kept with the process and the page table to indicate that the page is now in memory. 6. We restart the instruction that was interrupted by the illegal address trap. The process can now access the page as though it had always been in memory. Lecture 15 notes slide 2: 1. Page table has "present" (valid) bit. - If present, pointer to page frame in memory. - If not present, go to disk. 2. Hardware trpas to OS on reference to invalid page - (In MIPS/Nachos, trap on TLB miss, OS checks page table valid bit). 3. OS software a. Choose an old page to replace b. If old page has been modified, write contents back to disk c. Change its page table entry and TLB entry. d. Load new page into memory from disk e. Update page table entry f. Continue thread. Everything above is transparent: OS just runs another job in the meantime. TLB CACHING What happens on a TLB miss (everything from A to Z)?!!! Lecture 15 slide 2 1. TLB has a "present" (valid) bit. - If present, pointer to page frame in memory. - If not present, use software page table. 2. Hardware traps to OS on reference not in TLB 3. OS software: a. Check if page in memory. b. If yes, load page table entry into TLB. c. If no, perform page fault operation outlined above. d. continue thread. EFFECTIVE ACCESS TIME (EAT) IN TLB EAT = P(hit) * cost of hit + P(miss) * cost of miss 20 ns ==> TLB access 100 ns ==> Memory access P(hit) = .80 EAT = .80(120) + .20(220) = 140 ns --------------------------------------------------------------------------- PAGE REPLACEMENT IMPLEMENTATIONS --------------------------------------------------------------------------- -LRU APROXIMATION ALGORITHMS - Clock Page replacement algorithm - HW keeps use bit per page frame and sets on every reference - On page fault, advance clock hand, OS checks use bit 1 ==> clear use bit, continue 0 ==> replace page - Keep looping until we get a free page - Note that if clock hand goes all the way around (because all pages marked as 'used'), then on next sweep through these pages will be evicted. - N Chance Page Replacement algorithm - HW keeps use bit per page frame and sets on every reference - OS keeps counter per page frame - # of sweeps - On page fault, advance clock hand, OS checks use bit 1 ==> clear use bit, clear counter, continue 0 ==> increment counter, if (counter < N) continue else replace page - Second Chance List - Memory split into two parts - mapped - FIFO, marked r/w, directly accessible to program - unmapped - Second Chance List, LRU, marked invalid (but in memory) - On page fault, OS checks second chance list - if in SCL, move page from SCL to end of FIFO move page from head of FIFO to end of SCL set bits - if not in SCL, move page from disk to end of FIFO move page from head of FIFO to end of SCL move page form head of SCL to disk set bits --------------------------------------------------------------------------- VIRTUAL MEMORY AND PROJECT 3 --------------------------------------------------------------------------- GOOD READING ON VIRTUAL MEMORY - "Virtual Memory Management in the VAX/VMS Operating System", H.M. Levy, and P.H. Lipman. IEEE Computer. Vol. 15, No. 3 (March 1982), pp. 35-41. SOFTWARE-MANAGED TLB - Processor no longer sees page tables - Rather, it manages a (small) TLB: an array of type TranslationEntry int vpn int ppn boolean valid boolean readOnly boolean used boolean dirty (Size of TLB is only 4 entries!) - private TranslationEntry[4] translations in Machine.processor - On each memory reference, MIPS processor looks in TLB for matching entry and uses it if present - entry.vpn must be same as requested vpn, and entry.valid must be set - If no entry or not valid, an 'exceptionTLBMiss' is generated by the processor - If attempting to write and page is readOnly, an 'exceptionReadOnly' is generated --> Nothing you need to do about this but cleanly kill the process - Sets entry.used and entry.dirty (if writing) - For this project you will use a global INVERTED PAGE TABLE: - Maps to ppn - OK to use standard java.util.Hashtable (but don't depend on its synchronization properties!) - Dealing with a TLB miss - Get faulting vaddr from processor register - Look in inverted page table for ppn - Find invalid TLB entry (scan TLB) - If none, simply overwrite a random TLB entry - Write ppn to TLB entry - On context switch - Just set all TLB valid bits to false! DEMAND PAGING - Simulate much larger physical memory by using disk as backing store - Move contents of memory to/from disk as necessary to provide this illusion -> totally transparent to applications - Basic idea: - TLB miss causes lookup in page tables to find translation - If not in the inverted page table... - Try to allocate a free page - If no free pages, choose a page for eviction (This is where the clock algorithm comes in) - If evicted page is not dirty, just reuse it - If evicted page is dirty, write it to the swap file - Read faulting page in from swap file - Set valid bit of entry to true - Write entry to TLB - Return from TLB miss - Issues - Core map - The clock algorithm runs through page frames, so need ppn -> vpn mapping - Since the global page table only contains pages that are actually in physical memory, must maintain a separate data stucture for locating pages in swap - What if a page is in use by another process/thread? - I.e. we are doing a memory copy to/from the page, or loading it from disk? - Need to ensure these pages are not touched during page replacement - Page "pinning": keep it locked in physical memory for a short amount of time - What happens if all pages are "pinned" during sweep? - Need to sleep until page is no longer "pinned" - Format of swap file - Start out with a zero-length file - Every time we need new space, just grow swap file by one page - Reuse free pages (maintain linked-list of free entries) - When writing to swap: Find empty swap file page and write memory page to it, reset page table entry - When reading from swap: Find swap page number, read swap page into memory, reset page table entry EVALUATION - Evaluation of Page-Replacement Algorithm - Collect stats about page faults - Compare your page replacement policy with random