LogoMIPSI - MIPS Simulator


MIPSI is an instruction-level simulator for the MIPS family of processors. Its main attributes are simplicity and robustness - mipsi can run SPEC benchmarks as well as complicated, on-the-fly code generating programs such as the Standard ML of New Jersey without any modification. MIPSI runs on big or little endian MIPS boxes and on Alpha platforms. On mips based work stations, the slowdown due to simulation is about 65 times the speed of native code for most SPEC benchmarks. On an alpha 400 cross-simulating an R3000, the slowdown is roughly 4.


My goal in writing MIPSI was to investigate the amount of fine-grain instruction level parallelism available in C and ML programs, and then to find out if alternative garbage collection schemes could possibly increase the amount of parallelism. The garbage collector is responsible for the layout of data in garbage collected systems. Thus the decisions made by the garbage collector have a big impact on the cache performance of programs. On future architectures with speculative execution, such impact is amplified as the speculative forward progress of the processor is interrupted by cache misses.

Current Uses

More than 400 research projects have adopted MIPSI. Here is a sampling:

MIPSI has also been used in a wide variety of classes at the University of Washington. The undergraduate operating systems class has used MIPSI to teach students about virtual memory. The undergraduate architecture class has used MIPSI to investigate cache architectures, and the graduate architecture classes have used MIPSI to examine branch prediction behaviour, to measure instruction mix in C++ programs, and to compare superscalar and superpipelined architectures.

Frequently Asked Questions


You can DOWNLOAD MIPSI sources here.
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