CS 3410 Programming Assignment 2 FAQ Instructor: Kavita Bala PA2: Fully Pipelined MIPS Processor Due: Wednesday, October 22nd, 2008, 11:59 pm
October 20, 7:55pm: There have also been questions about the delay slot and the PC.  Here is some more detailed explaination.  The delay slot is an instruction-set (conceptual, logical) notion that stems from the hardware-reality of pipelining. In a pipelined processor, the "next" instruction is injected into the pipeline before the current instruction has finished executing. I say "next" because, due to the existence of branch and jump instructions, the processor *can't possibly know* what the real next instruction is until it finishes executing the current one (because the current instruction might be a branch or jump.) Injecting the next sequential instruction in memory is really the processor's "best guess" at the real next instruction. A consequence of this is that, when a branch or jump does occur, the "next instruction in sequential memory" has already been injected into the pipeline, even though it's not really the next instruction! So, in a pipelined processor, on a branch or jump, the processor is always forced to execute the "next instruction in sequential memory" after the branch/jump, before it can actually begin execution at the branch/jump's target location. Example (pseudocode): If memory looks like: JUMP TO WIN LOSE NOOP WIN Then the execution order will be: JUMP TO WIN LOSE WIN The delay slot is how the branch/jump instruction deals with this hardware problem. We say that LOSE is "in the delay slot" of the JUMP TO WIN instruction. In the pipelined MIPS standard, three things would happen with that delay slot: A.) It would execute.  (which is why LOSE happens before WIN above) B.) The PC would not update (from the JUMP TO WIN instruction) until after the delay-slot instruction (LOSE) had executed. C.) When the PC updated, it would be updated relative to the delay-slot instruction's address (LOSE) not the branch/jump instruction's address. October 20, 7:45pm: Several questions have been asked about calling conventions in writing the fibonacci implementations in PA2.  For that solution, we do not require you to implement the MIPS calling conventions exactly as described in lecture.  However, you are required to implement fibonacci recursively and in doing so you will have to correctly handle passing arguments, storing return values, etc.  To do this, even for a simple problem, you will have to adopt some sort of basic calling conventions and looking at the standard conventions is a very good place to start.  In call cases, you should ensure that your program is documented carefully enough so that we can easily understand how it works. October 18, 11:31am: The memory component in the assignment needs to be connected in a specific way to avoid errors.  The correct diagram is below.  You should wire you circuit as in this image.  Note specifically that, since it is word addressed, be sure to drop the lowest two bits from the address; as well as the extra high order bits. Note too, that a tri-state buffer to drives the bidirectional D pin which serves as both an input and an output of the RAM.
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