CS316 Programming Assignment 2: FAQ Instructor: Kavita Bala Due: Tuesday, September 25th, 2007, 11:59pm
6:00pm, September 25th: The cs316 Logisim library has been updated: the MIPS Program ROM component now understands the nop instruction. 3:00pm, September 24th: When execution reaches the end of the program, the PC should continue to increment by 4, executing beyond the end of the program. Don't worry about PC overflows. 5:00pm, September 23rd: A word on test programs: Comment the program as you would normally. We expect more comments than usual, though, since assembly is harder to read than most higher level languages. If (parts of) your program does anything meaningful, you should of course tell us what it does. In particular, comment any code that computes a simple result but is particularly convoluted for the purposes of exercising the processor. Register numbers ($1, $2, etc.) are not needed in comments. We can read them off the assembly code. Include values of registers in your comments if they are significant to your test (e.g., an instruction that tests sign extension of immediates). Your program does not have to do anything interesting, but tests that are easy to understand and easy to verify as being correct and complete will be greatly appreciated. 9:05pm, September 22nd: A value of 0 in bits 31-26 ("SPECIAL δ" in Table 1) indicates that you should look at bits 5-0 and execute the instruction according to Table 2. 8:50pm, September 22nd: A sample MIPS assembly program has been posted in the Tools section of the course homepage. 5:20pm, September 19th: The cs316 Logisim library has been updated with new components that you are required to use in PA2. Check here for details. 3:00pm, September 19th: PA2 has been updated. You are no longer required to compute jump addresses based on the delay slot's PC. 11:00pm, September 11th: There have been questions about the delay slot and the PC.  Here is some more detailed explaination.  The delay slot is an instruction-set (conceptual, logical) notion that stems from the hardware-reality of pipelining. In a pipelined processor, the "next" instruction is injected into the pipeline before the current instruction has finished executing. I say "next" because, due to the existence of branch and jump instructions, the processor *can't possibly know* what the real next instruction is until it finishes executing the current one (because the current instruction might be a branch or jump.) Injecting the next sequential instruction in memory is really the processor's "best guess" at the real next instruction. A consequence of this is that, when a branch or jump does occur, the "next instruction in sequential memory" has already been injected into the pipeline, even though it's not really the next instruction! So, in a pipelined processor, on a branch or jump, the processor is always forced to execute the "next instruction in sequential memory" after the branch/jump, before it can actually begin execution at the branch/jump's target location. Example (pseudocode): If memory looks like: JUMP TO WIN LOSE NOOP WIN Then the execution order will be: JUMP TO WIN LOSE WIN The delay slot is how the branch/jump instruction deals with this hardware problem. We say that LOSE is "in the delay slot" of the JUMP TO WIN instruction. In the pipelined MIPS standard, three things would happen with that delay slot: A.) It would execute. B.) The PC would not update (because of the JUMP TO WIN instruction) until after the delay-slot instruction (LOSE) had executed. C.) When the PC updated, it would be updated relative to the delay-slot instruction's address (LOSE), not the branch/jump instruction's address. We are only asking you to do the third, C. You do not have to execute the delay-slot instruction, and you can update the PC as soon as the branch/jump instruction executes. However, we ask that when you execute the jump, you compute the new memory address relative to the address of the delay-slot instruction, not the branch/jump instruction.
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