This project asks you to extend the datapath diagram that you created for Project 2. In particular, you must add support for division-by-zero exceptions and integer-overflow exceptions, as well as integrate a translation lookaside buffer into the memory stage of the MIPs pipeline. Once again, you will submit a Microsoft Visio worksheet and a report via CMS. The following describes each of the three additions to the processor.

1. Division-by-zero exceptions: When a divide-by-zero error occurs, the processor should save the current PC to the top of the stack and jump to a hard-wired address. The processor should also flush the instructions in the pipeline following the one that caused the exception to prevent them from executing. You may assume that the ALU has an output called DivBy0 that signals when a division by zero occurs.

   Note that this project asks you to implement exceptions differently than the way the textbook implements them. More precisely, your processor should not use an extra register for storing the PC value (called the EPC in the book). Instead, you must save the PC that caused the exception onto the top of the stack, and jump to a software handler at location 0xfc000000. You will need to introduce a new instruction, called rti, for return from interrupt, which reads a value from the top of the stack and stores it in the PC register.

2. Integer-overflow exceptions: Now assume that the ALU signals whether integer overflow occurs via output IntOver. If the ALU detects overflow, once again your processor must write the PC to the stack, flush the following instructions in the earlier stages of the pipeline, and jump to the same handler code. However, now that we've introduced another exception, we need some way of telling the handler the cause of the exception. The book introduces a new register called Cause for this purpose -- in this assignment, your processor should not introduce a new register, but should instead indicate the cause of the exception by setting register $4 ($a0) to 0 for division by zero and 1 for integer overflow. Once again, this requires saving the previous contents of $4 to the stack.

   Note that now your processor must save two registers to the stack when an exception occurs. Since the memory stage can only write one value to memory at a time, you'll effectively have to insert two new store instructions into the pipeline.

   Note also that you do not need to modify the rti instruction to restore register $4. If the $4 register needs to be restored, you may assume that the interrupt handler would do this in software prior to executing the rti instruction.

3. Translation lookaside buffer: Implement a TLB and add it to the memory stage of the pipeline, assuming that all memory addresses issued by the program are 32-bit virtual addresses. Your TLB should have six entries, which it manages according to a FIFO replacement policy. Assume that the machine uses 4KB pages and that physical memory is still 32-bit-addressable.

   When there's a TLB hit, the processor can use the translated physical address to access the requested byte from memory. When there's a TLB miss, the processor should stall and assume that a software-implemented page table provides the address translation and handles any page faults. The processor should then enter the virtual-to-physical mapping into the TLB, evicting the least-recently entered entry (FIFO). Once the TLB has been updated, the processor should restart the instruction that caused the TLB miss. Be sure to provide full details of the internal structure of the TLB.

The report

This project requires you to make more design decisions than the previous project. Therefore, be sure to document your design decisions in your report and explain the reasoning behind them.

What to submit