ECE/CS 314: Computer Organization Fall 2005
Project 2: MIPS Processor (Part 1: Datapath)
Due: Tuesday, December 6, 2005 at 11:59pm
  Basics
 

All ECE/CS 314 projects, including this one, are done in groups of exactly two students. Please link up with a partner and submit a single solution. If you do not have a partner yet and cannot find one, use the course newsgroup to find one.

Please read this document completely before starting.

  • You will submit this project electronically. See the end of this document for specific details.
  • The consultants can help you when you encounter problems. The consulting schedule is posted on the course web page. If you still have problems after talking to the consultants, you can try the course newsgroup, e-mail your questions to one of the TAs, or schedule an appointment.
  Project Goal
 

This part of the ECECS314 project has a single goal: to make sure you have thought through your entire pipelined MIPS datapath, including all the control signals and bypass paths.  Completing this document should be all the proof you need to convince yourself that your design works.

  Part 1: Datapath Design Drawing
 

The first part of this project is to draw a datapath diagram for your 5-stage pipelined MIPS processor implementation.

  • Instruction Fetch (IF)
  • Register fetch/decode instruction (shown as RD in the figure)
  • ALU/Execute (ALU, a.k.a. EX)
  • Memory (MEM)
  • Writeback (WB)

Each pipeline stage has a number of pipeline registers (shown in the figure above) immediately following the stage to save the computed values necessary for the next stage. Assume all pipeline registers are positive edge triggered, as described in lecture, and the PC and register file are negative edge triggered. The figure shows some values you will need to flop from one stage to another. You may flop additional values if you wish. Note: not all data-dependencies are shown in the figure above.

The MIPS register file and memory behave as described in the lecture notes.

You are to extend this figure to a complete datapath diagram. This will require you to add MUXes (and control signals) to route data as needed to implement all the required instructions, including all necessary bypass paths .

In addition to MUXes, your datapath diagram will need some additional parts – for example, an adder to be used in updating the PC, a sign-extension unit for immediate operands, and so forth.  You do not need to show the specifics of how these parts work, but you must include each as a block in your design.

Since branches are not resolved until they reach the EX stage, you must include a branch delay slot in your design.  This means that an instruction immediately following a branch must be executed regardless of whether the branch is taken or not.

You must show all the control signals needed to implement any of the required instructions.  However, you do not (yet) need to design the logic required to generate your control signals. That will come later.

Your datapath MUST be drawn using Microsoft Visio.  Visio is installed in the Phillips 318 and the CSUG labs.  To simplify the creation of your datapath diagram, we've created the following visio stencil and template:

ececs314 stencil - a group of parts that can be placed in the following template

ececs314 template - the starting point for your datapath diagram

  Part 2: Design Document
 

The design document consists of three parts:

  • Stage Description - describe what happens in each of the five stages (write a paragraph per stage, be specific).
  • Signal List - A complete list of each signal in your design and it's purpose.
  • Sample Execution - Show how the instruction set, described below, executes in your datapath. 

    Consider the following sequence of MIPS instructions:


    0x100:      sll    $0,$0,0 # nop
    0x104:      sll    $0,$0,0
    0x108:      sll    $0,$0,0
    0x10c:      sll    $0,$0,0
    0x110:      lw     $1,100($4) # assume value = 17
    0x114:      lui    $2,15
    0x118:      add    $1,$1,$2
    0x11c:      bgezal $1,skip
    0x120:      sub    $3,$1,$1
    0x124:      lui    $3,101
    0x128:skip: sw     $3,0($4)
    0x12c:      sll    $0,$0,0 # nop
    0x130:      sll    $0,$0,0
    0x134:      sll    $0,$0,0
    0x138:      sll    $0,$0,0
    Show how this instruction sequence would be executed using your datapath. Your answer should be a table giving the values of the control signals and important pipeline registers, just before the positive clock edge, for each cycle beginning when the lw instruction at location 0x110 and ending when the sw instruction at location 0x128 completes.

    This document can be either a .pdf, .doc or .txt file .

    •   Submitting Your Project
     

    You will submit this project electronically via CMS.  The electronic submission contains the following three files:
    Warning: Do NOT 'tar' or 'zip' your files before submitting to CMS.

    • README.txt
      As usual, the first few lines of this file must contain
      NAME: username1 username2
      Name of person1
      Name of person2
      PROJECT 2
      where username1 and username2 are the netids of you and your partner.
    • Datapath
      Your datapath drawing for Part 1. As stated above, this should be a Visio(tm) file, namely, datapath.vsd.
    • Design
      The design document of Part 2.  This includes: stage description, signal list, and sample execution.  Submit this as any of the following: design.pdf, design.doc or design.txt.