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Basics | |
All ECE/CS 314 projects, including this one, are done in groups of exactly two students. Please link up with a partner and submit a single solution. If you do not have a partner yet and cannot find one, use the course newsgroup to find one. Please read this document completely before starting.
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Project Goal | |
This part of the ECECS314 project has a single goal: to make sure you have thought through your entire pipelined MIPS datapath, including all the control signals and bypass paths. Completing this document should be all the proof you need to convince yourself that your design works. |
Part 1: Datapath Design Drawing | |
The first part of this project is to draw a datapath diagram for your 5-stage pipelined MIPS processor implementation.
Each pipeline stage has a number of pipeline registers (shown in the figure above) immediately following the stage to save the computed values necessary for the next stage. Assume all pipeline registers are positive edge triggered, as described in lecture, and the PC and register file are negative edge triggered. The figure shows some values you will need to flop from one stage to another. You may flop additional values if you wish. Note: not all data-dependencies are shown in the figure above. The MIPS register file and memory behave as described in the lecture notes. You are to extend this figure to a complete datapath diagram. This will require you to add MUXes (and control signals) to route data as needed to implement all the required instructions, including all necessary bypass paths . In addition to MUXes, your datapath diagram will need some additional parts – for example, an adder to be used in updating the PC, a sign-extension unit for immediate operands, and so forth. You do not need to show the specifics of how these parts work, but you must include each as a block in your design. Since branches are not resolved until they reach the EX stage, you must include a branch delay slot in your design. This means that an instruction immediately following a branch must be executed regardless of whether the branch is taken or not. You must show all the control signals needed to implement any of the required instructions. However, you do not (yet) need to design the logic required to generate your control signals. That will come later. Your datapath MUST be drawn using Microsoft Visio. Visio is installed in the Phillips 318 and the CSUG labs. To simplify the creation of your datapath diagram, we've created the following visio stencil and template: ececs314 stencil - a group of parts that can be placed in the following template ececs314 template - the starting point for your datapath diagram |
Part 2: Design Document | |
The design document consists of three parts:
Consider the following sequence of MIPS instructions: Show how this instruction sequence would be executed using your
datapath. Your answer should be a table giving the values of the control
signals and important pipeline registers, just before the positive clock edge,
for each cycle beginning when the lw instruction at location 0x110
and ending when the sw instruction at location 0x128 completes.
This document can be either a .pdf, .doc or .txt file . |
Submitting Your Project | |
You
will submit this project electronically via CMS. The electronic submission contains the following three files:
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