Please read this document completely before starting.

• The template files for this assignment are on the BSDCluster in /usr/class/ececs314/proj4.tar.gz. You can extract them in the usual way (note the files are in a different location than usual):

  cd ~
tar xzfv /usr/class/ececs314/proj4.tar.gz

  This creates a directory named ececs314/proj4 that contains template files for this assignment: Makefile, cpu.cast, ex.cast, if.cast, mem.cast, rd.cast, test.s, and wb.cast. Any existing files with these names will be overwritten–so rename them first.
• You will turn in this project electronically. See the end of this document for specific details.
• The consultants can help you when you encounter problems. The consulting schedule is posted on the course web page. If you still have problems after talking to the consultants, you can try the course newsgroup, e-mail your questions to one of the TAs, or schedule an appointment.

The goal of this part of the project is to build all datapath blocks for a pipelined MIPS processor. You will use the ALU you designed previously. To successfully complete this project, you will need to understand the following items:

• Datapath design
• The five-stage MIPS pipeline

We have posted a correct datapath drawing that you may use as a reference. You should look at this drawing and understand it, particularly in those areas (if any) where it differs from your own solution.

Note we do not require that the datapath you implement for this assignment exactly match the one you designed for the previous assignment (though we expect you may want to do this as a matter of pride), nor do we require that you implement our reference datapath. We just want you to implement a datapath that works correctly.

Design the required hardware for the MIPS ISA for each stage of the pipeline. Implement any multiplexers, other routing hardware, and computation blocks (other than the ALU, which you have already completed) necessary. You may omit any control signals necessary (like the register file control inputs, the memory control inputs, and all the MUX selection lines).

The template CAST files are:

• Instruction fetch (stage 1): if.cast
• Decode/operand fetch (stage 2): rd.cast
• Execute (stage 3): ex.cast
• Memory (stage 4): mem.cast
• Writeback (stage 5): wb.cast

Feel free to modify the body of the template definitions as well as the definition headers for these five stages, with a few exceptions. During part 4c we will specify that we need to be able to access certain buses and componenents such as c.rf for your regfile.  A complete list of buses needed for testing will be released with 4c.

Use your ALU in the definition of stage 3.

• Test each stage of the datapath by itself by setting the control signals you define by hand in irsim (Hint: use lots of script files :-) ). In some cases (like the instruction fetch as well as the memory), you may have to fake the memory output by setting it in irsim as well.
• For each stage, we expect to see both a test file and an irsim script file that can be used to test the stage by itself. We will expect to find the tests and scripts for each stage in files testif.cast, testif.cmd, testrd.cast, testrd.cmd, testex.cast, testex.cmd, testmem.cast, testmem.cmd, and testwb.cast, and testwb.cmd.
• The tests you perform must be documented in your README file.

The following provides additional information about each pipeline stage that might prove useful.

Instruction Fetch stage. You will need to interface with the CPU memory in order to fetch instructions. This will be handled in the final part of the project, and you can ignore this for the purposes of this assignment. Some things to keep in mind:

• The PC register must be flopped on the negative edge of the clock, and the bottom two bits of the PC are always zero. The template contains the skeleton for a 30-bit datapath for the PC update (see lecture notes for reasons).
• The next PC may be from a branch offset, jump target, or a register, or just PC+4. The module must contain the complete datapath necessary to implement this PC update.

Register Fetch/Decode stage. You do not need to implement the MIPS instruction decoding for this part.

Execute stage. This part contains the main logic of the processor. The EX() module will interface with the ALU. Branch condition evaluation should also be done in this stage, so that you can generate the correct signals to the next PC selection hardware. To implement all the specified instructions, you will need to be able to compare the two register operands for equality, inequality, and compare one of the registers to zero.  You must include any necessary bypass MUXes in your design, although the controls for the MUX are not required for this part of the project.

Memory stage. The interface to the memory itself will be added on in the final part of the project. However, you should be able to support the different types of load instructions.  You must include any necessary bypass MUXes in your design, although the controls for the MUX are not required for this part of the project.

Writeback stage. In this final stage a register is written with either the result from the ALU (flopped through the intervening stages) or the load from memory, or the link address (e.g. for jal).

Feel free to create other modules that you may need in separate CAST files. For instance, you may find that calculating the next PC value or computing a branch condition may need its own module.

Submission will be done using CMS .

In your ececs314/proj4 directory create a file named README. As usual, the first few lines of this file must contain

NAME: username1 username2
Name of person1
Name of person2
PROJECT 4.1

You will submit a single file: a tar archive containing all your cast and command files. Construct this as follows:


make clean 
proj4btar.314

The complete list of required MIPS instructions is: j, jal, beq, bne, blez, bgtz, addi, addiu, slti, sltiu, andi, ori, xori, lui, lb, lh, lw, lbu, lhu, sb, sh, sw, sll, srl, sra, sllv, srlv, srav, add, addu, sub, subu, and, or, xor, nor, slt, sltu, jr, jalr, bltz, bgez, bltzal, bgezal.