All ECE/CS 314 projects, including this one, are done in groups of exactly two students. Please link up with a partner and submit a single solution. If you do not have a partner yet and cannot find one, use the course newsgroup to find one.

Please read this document completely before starting.

• You will turn in an electronic and hard copy for this project. See the end of this document for specific details.
• The consultants can help you when you encounter problems. The consulting schedule is posted on the course web page. If you still have problems after talking to the consultants, you can try the course newsgroup, e-mail your questions to one of the TAs, or schedule an appointment.
• This is worth 20% of the final project.

This part of the ECECS314 project has a single goal: to make sure you have thought through your entire pipelined MIPS datapath, including all the control signals and bypass paths, before you write any CAST descriptions.  Completing this document should be all the proof you need to convice yourself that your design works.

The first part of this project is to draw a datapath diagram for your 5-stage pipelined MIPS processor implementation. The datapath should be capable of handling all the instructions implemented in your MIPS simulator from Project 2, with the exception of syscall . The instructions are listed at the end of this document for completeness.

The processor pipeline has the following 5 stages:

• Instruction Fetch (IF)
• Register fetch/decode instruction (shown as RD in the figure)
• ALU/Execute (ALU, a.k.a. EX)
• Memory (MEM)
• Writeback (WB)

Each pipeline stage has a number of pipeline registers (shown in the figure above) immediately following the stage to save the computed values necessary for the next stage. Assume all pipeline registers are positive edge triggered, as described in lecture, and the PC and register file are negative edge triggered. The figure shows some values you will need to flop from one stage to another. You may flop additional values if you wish. Note: not all data-dependencies are shown in the figure above.

The MIPS register file and memory behave as described in the lecture notes.

You are to extend this figure to a complete datapath diagram. This will require you to add MUXes (and control signals) to route data as needed to implement all the required instructions, including all necessary bypass paths .

In addition to MUXes, your datapath diagram will need some additional parts – for example, an adder to be used in updating the PC, a sign-extension unit for immediate operands, and so forth.

You must show all the control signals needed to implement any of the required instructions.  However, you do not (yet) need to design the logic required to generate your control signals. That will come later.

Your datapath MUST be drawn using Microsoft Visio.  Visio is installed in the Phillips 318 and the CSUG labs.  To simplify the creation of your datapath diagram, we've created the following visio stencil and template:

ececs314 stencil - a group of parts that can be placed in the following template

ececs314 template - the starting point for your datapath diagram

The design document consists of three parts:

Both an electronic copy, as well as a hard copy are required.  The hard copy is compiled as follow: title page, readme, datapath diagram, and design document.  The hard copy can be submitted during the lecture on Tuesday (November 23rd) or can be handed over to any of the TAs during the office hours. The electronic copy must be submitted through CMS by Monday November 22nd at 11:59 pm.  Your hard copy must exactly match the electronic copy submitted, an attempt to submit a more complete project in section, as compared to the electronic submission, will be considered cheating (no excuses will be accepted for this).

The electronic submission contains the following three files:

• README.txt
  As usual, the first few lines of this file must contain

  NAME: username1 username2
Name of person1
Name of person2
PROJECT 4a

  where username1 and username2 are the netids of you and your partner.
• Datapath
  Your datapath drawing for Part 1. As stated above, this should be a Visio(tm) file, namely, datapath.vsd.
• Design
  The design document of Part 2.  This includes: stage description, signal list, and sample execution.  Submit this as any of the following: design.pdf, design.doc or design.txt.

The complete list of required MIPS instructions is: j, jal, beq, bne, blez, bgtz, addi, addiu, slti, sltiu, andi, ori, xori, lui, lb, lh, lw, lbu, lhu, sb, sh, sw, sll, srl, sra, sllv, srlv, srav, add, addu, sub, subu, and, or, xor, nor, slt, sltu, jr, jalr, bltz, bgez, bltzal, bgezal.