• Inv() (node in, out): an inverter
• Nand2() (node a,b, out): a two-input NAND gate
• Nor2() (node a,b, out): a two-input NOR gate

• posFLOP() (node in, out) a positive edge-triggered flip-flop
• negFLOP() (node in, out) a negative edge-triggered flip-flop

The 314/parts.cast also defines five global signals:

• CLK: the global clock signal
• _CLK: the inverted version of the global clock signal
• Vdd: corresponds to the source of logic 1s (this signal is also aliased to the name TRUE)
• GND: corresponds to the source of logic 0s (this signal is also alised to the name FALSE)
• Reset: global reset signal

Vdd (TRUE) and GND (FALSE ) are also implictly included in your circuit whenever any building block is used. You may need these as sources of constant logic levels in your circuit.

Reset is a global signal that will be needed by every finite state machine. When a circuit is powered up, the first thing that happens is that this signal is set to logic 1 for some number of clock cycles. For this class, we will set Reset to 1 for 10 clock cycles. After that, Reset is set to 0 and the circuit should start functioning normally. FSMs use this signal to initialize any state-holding elements that must have well-defined values when the FSM starts. The following example shows how one might use a positive edge-triggered flip-flop and initialize it so that its initial value is 0:

import "314/parts.cast";   // import standard parts file

node in, out, _in, inreset; // declare signals

Inv() (in,_in);
Nor2() (Reset,_in, inreset);
/* "inreset" is 0 when "Reset" is 1, no matter what "in" is; 
    when "Reset" is 0, "inreset" is a copy of "in" */

posFLOP() (inreset,out);