Phillip Gibbons

Intel Labs

The goal of the Hi-Spade project is to enable a hierarchy-savvy approach to algorithm design and systems for emerging parallel hierarchies. Good performance often requires effective use of the cache/memory/storage hierarchy of the target computing platform.  Two recent trends---pervasive multi-cores and pervasive flash-based SSDs---provide both new challenges and new opportunities for maximizing performance.  The project seeks to create abstractions, tools and techniques that (i) assist programmers and algorithm designers in achieving effective use of emerging hierarchies and (ii) leads to systems that better leverage the new capabilities these hierarchies provide.  Our abstractions seek a sweet spot that exposes only what must be exposed for high performance, while our techniques deliver that good performance across a variety of platforms and platform-sharing scenarios.  Key enablers of our approach include internally-deterministic parallel programming, new cache abstractions, novel thread schedulers, and effective use of available flash devices (and other NVM technologies such as phase change memory).   Our performance evaluations consider a variety of application kernels involving sorting, graphs, geometry, graphics, string processing, and database operations.



Phillip B. Gibbons is a Principal Research Scientist at Intel Labs and Principal Investigator (together with Prof. Greg Ganger) for the new Intel Science and Technology Center for Cloud Computing, a $15M research partnership with Carnegie Mellon, Georgia Tech, Princeton, and UC Berkeley. He received his Ph.D. in Computer Science from the University of California at Berkeley in 1989. He joined Intel Labs (Intel Research) in 2001 after 11 years at (AT&T and Lucent) Bell Laboratories. His research areas include parallel computing, databases/data-intensive systems, sensor networks, cloud computing, distributed systems, and computer architecture. Gibbons’ publications span theory and systems, across a broad range of computer science (e.g., papers in ASPLOS, CIDR, JFP, PLDI, SIGMOD, SPAA, ToN, VLDBJ in 2010-11). His 125+ publications have been cited over 10,000 times, and include award-winning papers at ICDE, ISCA(2), NSDI, PLDI, and SIGMOD, as well as 13 other papers that were selected for “best papers” journal issues for their respective conferences (including ICFP, PODC, PODS, SIGCOMM, SPAA, and VLDB). Gibbons has served on 50+ international program committees, including being program chair/co-chair/vice-chair for the SPAA, SenSys, IPSN, ICDE, and DCOSS conferences.   He is an Associate Editor for the Journal of the ACM, and served as Chair of the Steering Committee for SPAA 2004-2007. He is an inventor on 17 U.S. Patents.  Gibbons is an Adjunct (Full) Professor in the Computer Science Department at Carnegie Mellon University.  He is a Fellow of the ACM.


B17 Upson Hall

Thursday, September 22, 2011

Refreshments at 3:45pm in the Upson 4th Floor Atrium


Computer Science


Spring 2011

Trumping the Multicore Memory

Hierarchy with Hi-Spade