Department of Computer Science Colloquium
Thursday January 31, 2002 4:15pm
Upson Hall B17
Designing a Small, High-Performing Load-Value Predictor
Computer Systems Laboratory
Microprocessors are becoming faster at such a rapid pace that the memory cannot keep up. As a result, the relative latency of load instructions grows constantly and already often impedes processor performance. Load-value predictors alleviate this problem by allowing the CPU to speculatively continue processing without having to wait for loads to complete, which can significantly improve execution speed.
This talk presents the evolution of a simple predictor into a progressively more effective hybrid load-value predictor. In particular, the techniques employed to improve the prediction accuracy, extend the coverage, and increase the capacity, all without increasing the predictor size, are discussed.
Cycle-accurate simulations of a four-way superscalar microprocessor running SPECint95 show that the presented predictor outperforms other predictors by 15% to 30% over a wide range of sizes. With 15kB of state, the smallest examined configuration, it matches or surpasses the speedups delivered by other, five times larger load-value predictors with both a re-fetch and a re-execute misprediction-recovery mechanism.