PDL: A High-Level Hardware Design Language for Pipelined Processors
June 2022, San Diego, California, USA
Processors are typically designed in Register Transfer Level (RTL) languages, which provide users with low-level control over circuit structure and timing. To achieve good performance, RTL designs are pipelined, with multiple instructions executing concurrently in different parts of the circuit. Thus even though processors implement a fundamentally sequential specification (the instruction set architecture), the implementation is highly concurrent and difficult to reason about. The interactions of multiple instructions—potentially speculative—can cause incorrect behavior.
We present PDL, a novel hardware description language targeted at the construction of pipelined processors. PDL provides one instruction at a time semantics; the first language to enforce that the generated pipelined circuit has the same behavior as a sequential specification, while still allowing users fine-grained control over performance-critical microarchitecture including timing of operations, data forwarding, and speculation. This enforcement enables design-space exploration. Adding or removing pipeline stages, moving operations from stage to stage, or otherwise changing pipeline structure normally requires careful analysis of bypass paths and stall logic; with PDL this analysis is handled by the compiler. We demonstrate the expressive power and ease of exploration in PDL by implementing several RISC-V cores with differing microarchitectures. Our results show that using PDL does not impose significant performance or area overhead compared to a standard HDL.
The final paper is not yet ready for distribution. It will be made available from this page.